Search results for "processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
49	Randolph D. Nelson, Donald F. Towsley, Asser N. Tantawi	Performance Analysis of Parallel Processing Systems.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
46	Edward H. Bensley, Thomas J. Brando, J. C. Fohlin, Myra Jean Prelle, Ann Wollrath	MITRE's future generation computer architectures program.	OOPSLA/ECOOP Workshop on Object-based Concurrent Programming	1988	DBLP DOI BibTeX RDF
46	Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal	Tiled Multicore Processors.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
46	James Laudon, Robert T. Golla, Greg Grohoski	Throughput-Oriented Multicore Processors.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
46	Mattan Erez, William J. Dally	Stream Processors.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
46	H. Peter Hofstee	Heterogeneous Multi-core Processors: The Cell Broadband Engine.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
46	Chuck Moore, Pat Conway	General-Purpose Multi-core Processors.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
46	Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang	Challenges in code generation for embedded processors.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
46	Peter Marwedel	Code generation for embedded processors: an introduction.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
46	Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens	Chess: retargetable code generation for embedded DSP processors.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
43	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors.	PPAM	2007	DBLP DOI BibTeX RDF	dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
43	Ruby B. Lee	Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures.	ASAP	2000	DBLP DOI BibTeX RDF	microSIMD, multimedia, microprocessors, computer arithmetic, permutations, processors, digital signal processors, Instruction Set Architecture, fine-grain parallelism, subword parallelism, media processors
43	Michael Yang, Ahmed N. Tantawy	A design methodology for protocol processors.	FTDCS	1995	DBLP DOI BibTeX RDF	protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
42	David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
40	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors.	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
39	Anurag Gupta, Ian F. Akyildiz, Richard Fujimoto	Performance Analysis of Time Warp With Multiple Homogeneous Processors.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	interacting processors, Time Warp protocol, discrete-state, continuous-time Markov chain model, exponential task times, timestamp increments, event message, negligible rollback, unbounded message buffers, homogeneous processors, processed events, rollback probability, uncommitted processed events, Time Warp testbed, performance evaluation, protocols, discrete event simulation, Markov processes, performance measures, multiprocessing systems, shared-memory multiprocessor, parallel simulation, speedup, communication delay, virtual time, state saving, probability mass function, probability distribution function
39	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors.	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
38	Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha	Optimizing Memory Transactions for Multicore Systems.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
38	Li-Shiuan Peh, Stephen W. Keckler, Sriram R. Vangal	On-Chip Networks for Multicore Systems.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
38	Doug Burger, Stephen W. Keckler, Simha Sethumadhavan	Composable Multicore Chips.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
38	Gurindar S. Sohi, T. N. Vijaykumar	Speculatively Multithreaded Architectures.	Multicore Processors and Systems	2009	DBLP DOI BibTeX RDF
38	Peter Marwedel, Gert Goossens (eds.)	Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994]	Code Generation for Embedded Processors	1995	DBLP BibTeX RDF
38	Henk Corporaal, Jan Hoogerbrugge	Code generation for transport triggered architectures.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Ulrich Bieker	Retargetable compilation of self-test programs using constraint logic programming.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus	Local microcode generation in system design.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Steven Novack, Alexandru Nicolau, Nikil D. Dutt	A Unified code generation approach using mutation scheduling.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Wolfgang Schenk	Retargetable code generation for parallel, pipelined processor structures.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Farhad Mavaddat	On transforming code generation to a parsing problem.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Marco Cornero, Filip Thoen, Gert Goossens, Francesco Curatelli	Software Synthesis for real-time information processing systems.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Paul Vanoostende, Etienne Vanzieleghem, Emmanuel Rousseau, Christian Massy, François Gérard	Retargetable code generation: key issues for successful introduction.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala	Flexware: A flexible firmware development environment for embedded systems.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Andreas Fauth	Beyond tool-specific machine descriptions.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Bernhard Wess	Code generation based on trellis diagrams.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
38	Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji	An ILP-based approach to code generation.	Code Generation for Embedded Processors	1994	DBLP BibTeX RDF
37	Pedro Marcuello, Antonio González 0001	Clustered speculative multithreaded processors.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	control-flow speculation, data value speculation, simultaneous multithreaded processors, dynamically scheduled processors, data dependance speculation, clustered processors
37	Bernard Goossens, Duc Thang Vu	Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.	ISPAN	1996	DBLP DOI BibTeX RDF	Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
37	Wade Walker, Harvey G. Cragon	Interrupt Processing in Concurrent Processors.	Computer	1995	DBLP DOI BibTeX RDF	Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts
36	Nuno Roma, Leonel Sousa	In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time.	CAMP	2000	DBLP DOI BibTeX RDF	specialized processors, high-order 2-D image moments, computational intensive task, systolic processing, programmable digital processors, configurable hardware logic, real-time system, image analysis, object modelling, floating-point arithmetic, digital signal processing chips, object matching
36	Stefan M. Petters	Bounding the execution time of real-time tasks on modern processors.	RTCSA	2000	DBLP DOI BibTeX RDF	task execution time, modern processors, embedded hard real time systems, up-to-date processors, fast core frequency, systematic information, real-time systems, computer architecture, complex systems, control flow graph, main memory, flow graphs, optimising compilers, real time tasks, acceleration techniques
36	Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu	Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors.	ISPAN	1996	DBLP DOI BibTeX RDF	edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
35	Rainer Leupers, Steven Bashford	Graph-based code selection techniques for embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions
35	Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman	Distributed cooperation in the absence of communication (brief announcement).	PODC	2000	DBLP DOI BibTeX RDF
33	Stephen W. Melvin, Yale N. Patt	Handling of packet dependencies: a critical issue for highly parallel network processors.	CASES	2002	DBLP DOI BibTeX RDF	memory synchronization, packet dependencies, parallel processing, network processors, processor architecture, thread level speculation, multithreaded processors, packet processing
33	Fuji Ren	Dialogue Machine Translation System Using Multiple Translation Processors.	DEXA Workshops	2000	DBLP DOI BibTeX RDF	dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation
33	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001	Trace Processors.	MICRO	1997	DBLP DOI BibTeX RDF	trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache
32	Amirali Baniasadi	Balancing clustering-induced stalls to improve performance in clustered processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clustering stalls, clustered processors
32	Tzi-cker Chiueh, Prashant Pradhan	Cache Memory Design for Network Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Routing Table Lookup, Caching, Network Processors
32	John-David Wellman, Edward S. Davidson	The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.	ICCD	1995	DBLP DOI BibTeX RDF	resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
32	Santanu Dutta, Wayne H. Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors.	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
31	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
31	Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson	Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors.	ISLPED	2007	DBLP DOI BibTeX RDF	FMAX distribution, parameter fluctuations, throughput distribution, multi-core, parameter variations
31	Dariusz R. Kowalski, Alexander A. Shvartsman	Writing-all deterministically and optimally using a non-trivial number of asynchronous processors.	SPAA	2004	DBLP DOI BibTeX RDF	write-all, distributed algorithms, shared memory, asynchrony, work
31	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
31	Byeong Kil Lee, Lizy Kurian John	NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors.	ICCD	2003	DBLP DOI BibTeX RDF
31	Peter R. Cappello	Multicore processors as Array Processors: Research Opportunities.	ASAP	2006	DBLP DOI BibTeX RDF
30	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications.	ICCS (1)	2008	DBLP DOI BibTeX RDF	quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
30	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
30	M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li	Adapting Tomasulo's algorithm for bytecode folding based Java processors.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming
30	A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans	TriMedia CPU64 Application Domain and Benchmark Suite.	ICCD	1999	DBLP DOI BibTeX RDF	TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing
30	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
30	Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu	CUBA: an architecture for efficient CPU/co-processor data communication.	ICS	2008	DBLP DOI BibTeX RDF	co-processors
30	Surendra Byna, Yong Chen 0001, Xian-He Sun	Taxonomy of Data Prefetching for Multicore Processors.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF	taxonomy of prefetching strategies, memory hierarchy, multicore processors, data prefetching
30	Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Mendel Rosenblum	Streamware: programming general-purpose multicore processors using streams.	ASPLOS	2008	DBLP DOI BibTeX RDF	general-purpose multicore processors, programming, streams, runtime system
30	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
30	Xiaotong Zhuang, Santosh Pande	Effective thread management on network processors with compiler analysis.	LCTES	2006	DBLP DOI BibTeX RDF	real-time scheduling, compiler optimizations, network processors, CPU scheduling
30	Naga K. Govindaraju, Nikunj Raghuvanshi, Dinesh Manocha	Fast and Approximate Stream Mining of Quantiles and Frequencies Using Graphics Processors.	SIGMOD Conference	2005	DBLP DOI BibTeX RDF	data streams, sorting, sliding windows, memory bandwidth, graphics processors, frequencies, quantiles
30	Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III	Scheduling for heterogeneous processors in server systems.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	scheduling, performance, power, heterogeneous processors
30	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
30	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
29	Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang	A self-timed redundant-binary number to binary number converter for digital arithmetic processors.	ICCD	1995	DBLP DOI BibTeX RDF	convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
29	Bhaskar Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis	The VLSI design and implementation of the array processors of a multilayer vision system architecture.	ASAP	1995	DBLP DOI BibTeX RDF	multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation
29	Kunal Agrawal, Charles E. Leiserson, Yuxiong He, Wen-Jing Hsu	Adaptive work-stealing with parallelism feedback.	ACM Trans. Comput. Syst.	2008	DBLP DOI BibTeX RDF	instantaneous parallelism, parallelism feedback, trim analysis, parallel computation, randomized algorithm, job scheduling, multiprogramming, processor allocation, multiprocessing, work-stealing, Adaptive scheduling, work, thread scheduling, adversary, span, space sharing, two-level scheduling
29	Bharadwaj Veeravalli, Wong Han Min	Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	finish times, communication delays, divisible loads, processing times, release times, Linear networks
29	Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman	Distributed Cooperation During the Absence of Communication.	DISC	2000	DBLP DOI BibTeX RDF
29	Ronny Krashinsky, Christopher Batten, Krste Asanovic	Implementing the scale vector-thread processor.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors
29	Mayan Moudgill, Stamatis Vassiliadis	Precise Interrupts.	IEEE Micro	1996	DBLP DOI BibTeX RDF	interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts
29	Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Jun'ichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada	PACS: A Parallel Microprocessor Array for Scientific Calculations	ACM Trans. Comput. Syst.	1983	DBLP DOI BibTeX RDF	highly parallel processors, multimicroprocessors, nearest neighbor communication, scientific calculation, distributed systems, parallel algorithms, synchronization, multiprocessors, performance measurement, supercomputer, parallel language, processor architecture, MIMD, array processors, multiprocessing, parallel processors
29	Kenneth E. Batcher	Bit-Serial Parallel Processing Systems.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors
29	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi	PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
29	Bogdan S. Chlebus, Dariusz R. Kowalski	Randomization Helps to Perform Tasks on Processors Prone to Failures.	DISC	1999	DBLP DOI BibTeX RDF
29	Jack L. Rosenfeld	A case study in programming for parallel-processors.	Commun. ACM	1969	DBLP DOI BibTeX RDF	Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network
28	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero	A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
28	Byeong Kil Lee, Lizy Kurian John	Implications of Programmable General Purpose Processors for Compression/Encryption Applications.	ASAP	2002	DBLP DOI BibTeX RDF
28	Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey	Processors for Mobile Applications.	ICCD	2000	DBLP DOI BibTeX RDF
28	Lin Chen 0001	Optimal overlap representations.	ISPAN	1996	DBLP DOI BibTeX RDF	optimal overlap representations, minimal interval, circular arc overlap representations, minimal interval overlap representation, EREW PRAM processors, common CRCW PRAM, BSR processors, parallel algorithms, computational complexity, computational geometry, optimal algorithms
28	David Goodwin, Darin Petkov	Automatic generation of application specific processors.	CASES	2003	DBLP DOI BibTeX RDF	automatic instruction-set generation, ASIPs, configurable processors, extensible processors
28	Jorge E. Carrillo, Paul Chow	The effect of reconfigurable units in superscalar processors.	FPGA	2001	DBLP DOI BibTeX RDF	OneChip, superscalar processors, reconfigurable processors
28	Sang Jeong Lee, Yuan Wang, Pen-Chung Yew	Decoupled Value Prediction on Trace Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction
28	Joseph A. Fisher	Customized Instruction-Sets for Embedded Processors.	DAC	1999	DBLP DOI BibTeX RDF	custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors
28	Pedro Marcuello, Antonio González 0001, Jordi Tubella	Speculative Multithreaded Processors.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF	multithreaded processors, data speculation, dynamically scheduled processors, data dependence speculation, control speculation
28	Sandeep N. Bhatt, Geppino Pucci, Abhiram G. Ranade, Arnold L. Rosenberg	Scattering and Gathering Messages in Networks of Processors.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	message scattering, messages gathering, networks of processors, trees of processors, noncolliding paths, queueing mechanisms, scheduling, distributed processing, multiprocessor interconnection networks, spanning trees, buffering
28	Ashok K. Agrawala, Edward G. Coffman Jr., M. R. Garey, Satish K. Tripathi	A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	uniform processor systems, Consider a set of processors P1, ..., Pm differing only in speed and a set of jobs with exponentially distributed execution times, The rate parameter for the ith processor is given by ?i, 1 =i = m, where we assume the processors are ordered so that ?1 = ?2 = ... = ?m. The problem is to sequence the jobs nonpreemptively so as to minimize expected total flow time (sum of finishing times). We defin, Mean flow time minimization, stochastic optimization, stochastic scheduling, routing problems
28	Chris R. Jesshope	Some Results Concerning Data Routing in Array Processors.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	data rotation, ICL distributed array processor (DAP), k-dimensional cyclic networks, Array processors, parallel processors, data routing
27	Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero	A first glance at Kilo-instruction based multiprocessors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
27	Emile Haddad	Optimal load distribution for asynchronously scheduled homogeneous multiprocessor and distributed systems.	HICSS (2)	1995	DBLP DOI BibTeX RDF	optimal load distribution, asynchronously scheduled homogeneous multiprocessor systems, interacting tasks, identical processors, job completion time minimization, execution initiation times, earliest availability, load parameters, optimal load allocation, uneven module distribution, distributed systems, resource allocation, distributed processing, multiprocessing systems, processor scheduling, minimisation, system parameters, processor assignment
27	Ning Weng, Tilman Wolf	Analytic modeling of network processors for parallel workload mapping.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	embedded systems, network processors, multiprocessor scheduling, Application profiling
27	Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha	Throughput optimal task allocation under thermal constraints for multi-core processors.	DAC	2009	DBLP DOI BibTeX RDF	optimal throughput, task allocation, thermal management, multi-core processors, thread migration
27	Garo Bournoutian, Alex Orailoglu	Miss reduction in embedded processors through dynamic, power-friendly cache design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic associativity, multi-core, embedded processors, data cache
27	Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao	Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.	DAC	2008	DBLP DOI BibTeX RDF	subgraph covering, VLIW, ASIPs, extensible processors
27	Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju	A Throughput-Driven Task Creation and Mapping for Network Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF	Intel IXP, Task Creation and Mapping, Throughput, Network Processors, Dataflow Programming