Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
118	Jinpyo Park, Je-Hyung Lee, Soo-Mook Moon	Register Allocation for Banked Register File.	LCTES/OM	2001	DBLP DOI BibTeX RDF	banked register file, register allocation
109	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
108	Yoonseo Choi, Hwansoo Han	Optimal register reassignment for register stack overflow minimization.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	register stack, sequence graph, register allocation, Register assignment
102	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero	Speculative early register release.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	physical register release, optimization, register file, register renaming
92	André Seznec, Eric Toullec, Olivier Rochecouste	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.	MICRO	2002	DBLP DOI BibTeX RDF
89	Minwook Ahn, Yunheung Paek	Register coalescing techniques for heterogeneous register architecture with copy sifting.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing
83	Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang	Register Allocation on Stream Processor with Local Register File.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	local register file, spilling, register allocation, VLIW, stream processor
82	G. X. Tyson, M. Smelyanskyi, Edward S. Davidson	Evaluating the Use of Register Queues in Software Pipelined Loops.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW
82	Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang	Inter-procedural stacked register allocation for itanium® like architecture.	ICS	2003	DBLP DOI BibTeX RDF	hot region, inter-procedural stacked register allocation, quota assignment, register allocation, hotspot
81	Robert Yung, Neil C. Wilhelm	Caching processor general registers.	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
80	Rama Sangireddy	Register Organization for Enhanced On-Chip Parallelism.	ASAP	2004	DBLP DOI BibTeX RDF
77	Minwook Ahn, Jooyeon Lee, Yunheung Paek	Optimistic coalescing for heterogeneous register architectures.	LCTES	2007	DBLP DOI BibTeX RDF	heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors
76	Guei-Yuan Lueh, Thomas R. Gross, Ali-Reza Adl-Tabatabai	Fusion-based register allocation.	ACM Trans. Program. Lang. Syst.	2000	DBLP DOI BibTeX RDF	performance evaluation, register allocation
75	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Early Register Release for Out-of-Order Processors with RegisterWindows.	PACT	2007	DBLP DOI BibTeX RDF
75	Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi	Physical Register Inlining.	ISCA	2004	DBLP DOI BibTeX RDF
72	Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev	Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure.	MICRO	2004	DBLP DOI BibTeX RDF
72	Jun Yan 0008, Wei Zhang 0002	Compiler-guided register reliability improvement against soft errors.	EMSOFT	2005	DBLP DOI BibTeX RDF	register lifetime, reliability, soft errors, register file
72	José-Lorenzo Cruz, Antonio González 0001, Mateo Valero, Nigel P. Topham	Multiple-banked register file architectures.	ISCA	2000	DBLP DOI BibTeX RDF	bypass logic, register file architecture, register file cache, dynamically-scheduled processor
70	Masaaki Kondo, Hiroshi Nakamura	A Small, Fast and Low-Power Register File by Bit-Partitioning.	HPCA	2005	DBLP DOI BibTeX RDF
68	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
68	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design.	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
67	Liem Tran, Nicholas Nelson 0001, Fung Ngai, Steve Dropsho, Michael C. Huang 0001	Dynamically reducing pressure on the physical register file through simple register sharing.	ISPASS	2004	DBLP DOI BibTeX RDF
67	Ivan D. Baev, Richard E. Hank, David H. Gross	Prematerialization: reducing register pressure for free.	PACT	2006	DBLP DOI BibTeX RDF	rematerialization, register allocation, VLIW, Itanium, register pressure
67	Sid Ahmed Ali Touati	Register Saturation in Instruction Level Parallelism.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure
67	Xiaotong Zhuang, Santosh Pande	Differential register allocation.	PLDI	2005	DBLP DOI BibTeX RDF	architected register, differential dncoding, register allocation
67	Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens	Register Organization for Media Processing.	HPCA	2000	DBLP DOI BibTeX RDF	register organization, register architecture, processor architecture, media processors
66	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
66	Montserrat Ros, Peter Sutton	A post-compilation register reassignment technique for improving hamming distance code compression.	CASES	2005	DBLP DOI BibTeX RDF	register reassignment, hamming distance, code compression
66	Christian Wimmer, Hanspeter Mössenböck	Optimized interval splitting in a linear scan register allocator.	VEE	2005	DBLP DOI BibTeX RDF	linear scan, java, optimization, compilers, graph-coloring, register allocation, just-in-time compilation
66	Michael D. Smith 0001, Norman Ramsey, Glenn H. Holloway	A generalized algorithm for graph-coloring register allocation.	PLDI	2004	DBLP DOI BibTeX RDF	graph coloring, register allocation
65	Xuan Guan, Yunsi Fei	Reducing power consumption of embedded processors through register file partitioning and compiler support.	ASAP	2008	DBLP DOI BibTeX RDF
65	Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose	Increasing Processor Performance Through Early Register Release.	ICCD	2004	DBLP DOI BibTeX RDF
65	Ulrich Hirnschrott, Andreas Krall, Bernhard Scholz	Graph Coloring vs. Optimal Register Allocation for Optimizing Compilers.	JMLC	2003	DBLP DOI BibTeX RDF
65	Xianglong Huang, Steve Carr 0001, Philip H. Sweany	Loop Transformations for Architectures with Partitioned Register Banks.	LCTES/OM	2001	DBLP DOI BibTeX RDF
64	Nicola Zingirian, Massimo Maresca	Selective Register Renaming: A Compiler-Driven Approach to Dynamic Register Renaming.	HPCN	2001	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Instruction Level Parallelism, Register Allocation, Loop Parallelization
62	David W. Wall	Register Windows versus Register Allocation.	PLDI	1988	DBLP DOI BibTeX RDF
62	David W. Wall	Register windows vs. register allocation (with retrospective)	Best of PLDI	1988	DBLP DOI BibTeX RDF
62	Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung	SCRF - A Hybrid Register File Architecture.	PaCT	2007	DBLP DOI BibTeX RDF	cluster processor architecture, register architecture, register allocation algorithm, VLIW processor
62	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	register requirements, register file organization, clustered organization, Modulo scheduling, spill code
62	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
62	Nicola Zingirian, Massimo Maresca	Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs.	HPCN	2000	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization
61	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
61	Peter Koepke, Russell G. Miller	An Enhanced Theory of Infinite Time Register Machines.	CiE	2008	DBLP DOI BibTeX RDF	ordinal computability, hypercomputation, infinitary computation, register machine
61	Jason Cong, Yiping Fan, Wei Jiang	Platform-based resource binding using a distributed register-file microarchitecture.	ICCAD	2006	DBLP DOI BibTeX RDF	distributed register file, behavior synthesis, resource binding
61	Xiaotong Zhuang, Santosh Pande	Balancing register allocation across threads for a multithreaded network processor.	PLDI	2004	DBLP DOI BibTeX RDF	register allocation, network processor, multithreaded processor
61	Akira Koseki, Hideaki Komatsu, Toshio Nakatani	Preference-Directed Graph Coloring.	PLDI	2002	DBLP DOI BibTeX RDF	irregular-register architectures, graph coloring, register allocation, register coalescing
60	V. Krishna Nandivada, Fernando Magno Quintão Pereira, Jens Palsberg	A Framework for End-to-End Verification and Evaluation of Register Allocators.	SAS	2007	DBLP DOI BibTeX RDF
60	Raid Ayoub, Alex Orailoglu	Power efficient register file update approach for embedded processors.	ICCD	2007	DBLP DOI BibTeX RDF
60	Rakesh Nalluri, Rohan Garg 0003, Preeti Ranjan Panda	Customization of Register File Banking Architecture for Low Power.	VLSI Design	2007	DBLP DOI BibTeX RDF
60	Rama Sangireddy	Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors.	ITNG	2006	DBLP DOI BibTeX RDF
60	Rama Sangireddy, Arun K. Somani	Exploiting Quiescent States in Register Lifetime.	ICCD	2004	DBLP DOI BibTeX RDF
60	Xiaotong Zhuang, Santosh Pande	Resolving Register Bank Conflicts for a Network Processor.	IEEE PACT	2003	DBLP DOI BibTeX RDF
60	Sriraman Tallam, Rajiv Gupta 0001	Bitwidth aware global register allocation.	POPL	2003	DBLP DOI BibTeX RDF	minimal bitwidth, packing interfering nodes, subword data, embedded applications
60	Sid Ahmed Ali Touati, Christine Eisenbeis	Early Control of Register Pressure for Software Pipelined Loops.	CC	2003	DBLP DOI BibTeX RDF
58	Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev	Reducing register pressure in SMT processors through L2-miss-driven early register release.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	register file, Simultaneous multithreading
58	Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures
58	Akira Koseki, Yoshiaki Fukazawa, Hideaki Komatsu	A Register Allocation Technique Using Register Existence Graph.	ICPP	1997	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Program Dependence Graph, Code Scheduling
58	Guido Araujo, Sharad Malik	Optimal code generation for embedded memory non-homogeneous register architectures.	ISSS	1995	DBLP DOI BibTeX RDF	TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation
57	Jason Hiser, Steve Carr 0001, Philip H. Sweany, Steven J. Beaty	Register Assignment for Software Pipelining with Partitioned Register Banks.	IPDPS	2000	DBLP DOI BibTeX RDF
57	Miquel Huguet, Tomás Lang	Architectural Support for Reduced Register Saving / Restoring in Single-Window Register Files.	ACM Trans. Comput. Syst.	1991	DBLP DOI BibTeX RDF
57	Suhyun Kim, Soo-Mook Moon	Rotating register allocation with multiple rotating branches.	ICS	2008	DBLP DOI BibTeX RDF	rotating register, register allocation, software pipelining
57	Byung-Sun Yang, Junpyo Lee, SeungIl Lee, Seongbae Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman, Soo-Mook Moon	Efficient Register Mapping and Allocation in LaTTe, an Open-Source Java Just-in-Time Compiler.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	register mapping, copy coalescing, Java virtual machine, register allocation, just-in-time compilation
57	Hui Zeng, Kanad Ghose	Register file caching for energy efficiency.	ISLPED	2006	DBLP DOI BibTeX RDF	register caching, energy-efficiency, register files
56	Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev 0001	Energy-efficient renaming with register versioning.	ISLPED	2009	DBLP DOI BibTeX RDF	microprocessor, register renaming
56	Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee	Enabling compiler flow for embedded VLIW DSP processors with distributed register files.	LCTES	2007	DBLP DOI BibTeX RDF	distributed register files, embedded VLIW DSP compilers, software pipelining
56	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
56	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
56	Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen	Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	architecture, register file, simultaneous multithreading, Multithreaded architecture
56	Srinivas Katkoori, Ranga Vemuri, Jay Roy	A Hierarchical Register Optimization Algorithm for Behavioral Synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	Register Optimization, High Level Synthesis, Life-cycle Analysis
56	Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.	HASE	2008	DBLP DOI BibTeX RDF
56	Shuai Wang 0006, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras	Asymmetrically Banked Value-Aware Register Files.	ISVLSI	2007	DBLP DOI BibTeX RDF
56	JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally	Register pointer architecture for efficient embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
56	Soontae Kim	Reducing ALU and Register File Energy by Dynamic Zero Detection.	IPCCC	2007	DBLP DOI BibTeX RDF
56	Rahul Nagpal, Y. N. Srikant	Register File Energy Optimization for Snooping Based Clustered VLIW Architectures.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
56	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Aneesh Aggarwal	Address-Value Decoupling for Early Register Deallocation.	ICPP	2006	DBLP DOI BibTeX RDF
56	Sid Ahmed Ali Touati	On the Optimality of Register Saturation.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
56	Bengu Li, Youtao Zhang, Rajiv Gupta 0001	Speculative Subword Register Allocation in Embedded Processors.	LCPC	2004	DBLP DOI BibTeX RDF
56	J. Adam Butts, Gurindar S. Sohi	Use-Based Register Caching with Decoupled Indexing.	ISCA	2004	DBLP DOI BibTeX RDF
56	Il Park 0001, Michael D. Powell, T. N. Vijaykumar	Reducing register ports for higher speed and lower energy.	MICRO	2002	DBLP DOI BibTeX RDF
56	R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen	Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF
56	C. P. Ravikumar, R. Aggarwal, C. Sharma	A Graph-Theoretic Approach for Register File Based Synthesis.	VLSI Design	1997	DBLP DOI BibTeX RDF
55	Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg	Virtual machine showdown: Stack versus registers.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	register architecture, stack architecture, virtual machine, Interpreter
53	Thomas Scholz, Michael Schäfers 0003	An improved dynamic register array concept for high-performance RISC processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing
52	Jie S. Hu, Shuai Wang 0006, Sotirios G. Ziavras	In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.	DSN	2006	DBLP DOI BibTeX RDF
52	Feng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang	A Register Allocation Framework for Banked Register Files with Access Constraints.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
52	Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001	Register Isolation for Synthesizable Register Files.	PATMOS	2004	DBLP DOI BibTeX RDF
52	Fernando Magno Quintão Pereira, Jens Palsberg	Register allocation by puzzle solving.	PLDI	2008	DBLP DOI BibTeX RDF	puzzle solving, register aliasing, register allocation
52	Florent Bouchez, Alain Darte, Fabrice Rastello	Advanced conservative and optimistic register coalescing.	CASES	2008	DBLP DOI BibTeX RDF	coloring number, greedy-k-colorable graph, register allocation, chordal graph, register coalescing
52	Sid Ahmed Ali Touati	On the Periodic Register Need in Software Pipelining.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining
52	Jian Wang 0046, Andreas Krall, M. Anton Ertl, Christine Eisenbeis	Software pipelining with register allocation and spilling.	MICRO	1994	DBLP DOI BibTeX RDF	instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling
52	Minwook Ahn, Yunheung Paek	Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF	heterogeneous register architecture, register aliasing, compiler, code generation, register allocation, register coalescing
51	Christian Wimmer, Michael Franz	Linear scan register allocation on SSA form.	CGO	2010	DBLP DOI BibTeX RDF	SSA form deconstruction, lifetime analysis, linear scan, Java, register allocation, just-in-time compilation, SSA form
51	Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	LCTES	2008	DBLP DOI BibTeX RDF	register allocation, placement and routing, coarse-grained, reconfigurable arrays
51	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
51	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
51	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
51	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	optimization, Code generation, low-power design, graph partitioning, embedded processor, retargetable compilers, spill code, instruction encoding, register window
51	Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy	An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications
51	Bernhard Scholz, Erik Eckstein	Register allocation for irregular architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	boolean quadratic problem, register allocation
51	Jun Yan 0008, Wei Zhang 0002	Exploiting virtual registers to reduce pressure on real registers.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	short-lived variables, virtual register, register allocation, Register file, data forwarding