Search results for "retargetable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A SIMD optimization framework for retargetable compilers.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	SIMD, vectorization, ASIP, subword parallelism, retargetable compilers
98	Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren 0001	Retargetable code optimization with SIMD instructions.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	SIMD, vectorization, subword parallelism, retargetable compilers
74	Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001	A retargetable framework for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm
70	Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens	Processor modeling and code selection for retargetable compilation.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	code selection, graph instruction set graph, retargetable code generation, embedded systems, system design, retargetable compilation, processor modeling
66	Emilio Wuerges, Luiz C. V. dos Santos, Olinto J. V. Furtado, Sandro Rigo	An early real-time checker for retargetable compile-time analysis.	SBCCI	2009	DBLP DOI BibTeX RDF	compile-time WCET analysis, time-constraint feasibility analysis
66	Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh	Retargetable Code Optimization for Predicated Execution.	DATE	2008	DBLP DOI BibTeX RDF
66	Sejong Oh, Yunheung Paek	A Quantitative Comparison of Two Retargetable Compilation Approaches.	ICPP	2003	DBLP DOI BibTeX RDF
66	Jay W. Warfield, Henry R. Bauer III	An expert system for a retargetable peephole optimizer.	ACM SIGPLAN Notices	1988	DBLP DOI BibTeX RDF
63	Heekyung Kim, Dukyoung Yun, Soonhoi Ha	Scalable and retargetable simulation techniquesfor multiprocessor systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	simulation, scalable, parallel, distributed, multiprocessor, retargetable
63	Jason Hiser, Jack W. Davidson	EMBARC: an efficient memory bank assignment algorithm for retargetable compilers.	LCTES	2004	DBLP DOI BibTeX RDF	partition assignment, embedded systems, retargetable compilers
59	Hans M. Mulder, Robert J. Portier	Cost-effective design of application specific VLIW processors using the SCARCE framework.	MICRO	1989	DBLP DOI BibTeX RDF
55	Lothar Nowak, Peter Marwedel	Verification of Hardware Descriptions by Retargetable Code Generation.	DAC	1989	DBLP DOI BibTeX RDF
51	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001	A Retargetable Software Timing Analyzer Using Architecture Description Language.	ASP-DAC	2007	DBLP DOI BibTeX RDF	retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis
51	Wei Qin, Joseph D'Errico, Xinping Zhu	A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	retargetable, instruction set simulator, compiled simulation
51	Hoonmo Yang, Moonkey Lee	Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator
51	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation
51	Lukai Cai, Andreas Gerstlauer, Daniel Gajski	Retargetable profiling for rapid, early system-level design space exploration.	DAC	2004	DBLP DOI BibTeX RDF	profiling, exploration, system level design, retargetable
51	Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt	An efficient retargetable framework for instruction-set simulation.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm
51	Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau	Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC
51	Scott R. Tilley	Domain-retargetable reverse engineering. III. Layered modeling.	ICSM	1995	DBLP DOI BibTeX RDF	layered modeling, domain-retargetable reverse engineering, structural understanding, large information spaces, reverse engineering, relational databases, software maintenance, software tools, conceptual modeling, tools, hypertext, artifacts
51	Robert A. Mueller, Michael R. Duda, Philip H. Sweany, Jack S. Walicki	Horizon: A Retargetable Compiler for Horizontal Microarchitectures.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	horizontal microarchitectures, vertical migration, complex application code, horizontal microcode, optimized microcode, concurrency, abstraction, timing, program compilers, microprogramming, retargetable compiler, assembly languages, Horizon
47	Yong-Kyu Jung	Fault-recovery Non-FPGA-based Adaptable Computing System Design.	AHS	2007	DBLP DOI BibTeX RDF
43	José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos	An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code.	SAMOS	2007	DBLP DOI BibTeX RDF
43	Dan Wu, Zhiying Wang 0003, Kui Dai	Retargetable Machine-Description System: Multi-layer Architecture Approach.	GCC	2005	DBLP DOI BibTeX RDF
43	Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang	RCGES: Retargetable Code Generation for Embedded Systems.	ATVA	2004	DBLP DOI BibTeX RDF
43	Gabriele Luculli	An ISA-Retargetable Framework for Embedded Software Analysis.	ECBS	2003	DBLP DOI BibTeX RDF
43	Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji	Design Retargetable Platform System for Microprocessor Functional Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
43	Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery	FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors.	EMSOFT	2002	DBLP DOI BibTeX RDF
43	Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama	A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
43	Rajiv A. Ravindran, Rajat Moona	Retargetable Cache Simulation Using High Level Processor Models.	ACSAC	2001	DBLP DOI BibTeX RDF
43	B. S. Visser	A Framework for Retargetable Code Generation Using Simulated Annealing.	EUROMICRO	1999	DBLP DOI BibTeX RDF
43	Silvina Hanono, Srinivas Devadas	Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
43	David Ung, Cristina Cifuentes	SRL 3/4-A Simple Retargetable Loader.	Australian Software Engineering Conference	1997	DBLP DOI BibTeX RDF
43	Thomas M. Morgan, Lawrence A. Rowe	Analyzing Exotic Instructions for a Retargetable Code Generator.	SIGPLAN Symposium on Compiler Construction	1982	DBLP DOI BibTeX RDF
39	Francesco Papariello, Gabriele Luculli	Optimization of a Retargetable Functional Simulator for Embedded Processors.	ECBS	2002	DBLP DOI BibTeX RDF	retargetable ISS, platform design, system-on-chip, embedded processors, system-level design
39	John H. Shamilian, Henry S. Baird, Thomas L. Wood	A retargetable table reader.	ICDAR	1997	DBLP DOI BibTeX RDF	retargetable table reader, machine-printed documents, predefined tabular-data layout, textual data, record lines, fixed-width fields, field-specific contextual knowledge, small print, tight line-spacing, photocopies, line-art, background patterns, pitch-estimation, high-performance OCR, segmentation, graphical user interface, neural nets, document image processing, skew-correction
39	Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya	Industrial experience using rule-driven retargetable code generation for multimedia applications.	ISSS	1995	DBLP DOI BibTeX RDF	VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio
35	Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren 0001	A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.	DATE	2004	DBLP DOI BibTeX RDF
35	Norman Ramsey, Jack W. Davidson	Machine Descriptions to Build Tools for Embedded Systems.	LCTES	1998	DBLP DOI BibTeX RDF
31	João Dias, Norman Ramsey	Automatically generating instruction selectors using declarative machine descriptions.	POPL	2010	DBLP DOI BibTeX RDF	declarative machine descriptions, retargetable compilers, instruction selection
31	Xinping Zhu, Sharad Malik	A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation
31	Florian Brandner, Dietmar Ebner, Andreas Krall	Compiler generation from structural architecture descriptions.	CASES	2007	DBLP DOI BibTeX RDF	ADL, architecture description, retargetable compiler
31	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Operation tables for scheduling in the presence of incomplete bypassing.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hazard detection, operation table, reservation table, scheduling, retargetable compilers, bypass
31	Ronan Amicel, François Bodin	Mastering Startup Costs in Assembler-Based Compiled Instruction-Set Simulation.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	compiled instruction-set simulation, embedded systems, high performance, assembler, development tools, retargetable
31	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
31	Young Geol Kim, Tag Gon Kim	A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Rapid prototyping, ASIP, Design reuse, Architecture description, Retargetable simulator
31	Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto	The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.	ISSS	1996	DBLP DOI BibTeX RDF	virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling
31	Eero Lassila	A Macro Expansion Approach to Embedded Processor Code Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	macro expansion approach, embedded processor code generation, embedded special-purpose processors, retargetable assembly-code-level macro expander, program flow analysis, hierarchical macro libraries, compiler writer, assembly language programmer, computer architecture
31	Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek	A retargetable parallel-programming framework for MPSoC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	parallel-programming, design-space exploration, Embedded software, multiprocessor system on chip, software generation
31	Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang	Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF
31	Max R. de O. Schultz, Alexandre Keunecke Ignácio Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. dos Santos	A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems.	SAMOS	2007	DBLP DOI BibTeX RDF
31	Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu	Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow.	DATE	2007	DBLP DOI BibTeX RDF
31	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Retargetable pipeline hazard detection for partially bypassed processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	K. Vasanta Lakshmi, Deepak Sreedhar, Easwaran Raman, Priti Shankar	Integrating a New Cluster Assignment and Scheduling Algorithm into an Experimental Retargetable Code Generation Framework.	HiPC	2005	DBLP DOI BibTeX RDF
31	Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana	A retargetable register allocation framework for embedded processors.	LCTES	2004	DBLP DOI BibTeX RDF	register allocation, embedded processors
31	Xinping Zhu, Sharad Malik	Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing.	DATE	2004	DBLP DOI BibTeX RDF
31	Hoonmo Yang, Moonkey Lee	Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme.	CIS	2004	DBLP DOI BibTeX RDF
31	Wei Qin, Sharad Malik	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.	DATE	2003	DBLP DOI BibTeX RDF
31	Daniel Kästner	TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses.	GPCE	2003	DBLP DOI BibTeX RDF
31	Wei Qin, Sharad Malik	Automated synthesis of efficient binary decoders for retargetable software toolkits.	DAC	2003	DBLP DOI BibTeX RDF	binary decoder, decoding tree, decision tree, instruction set simulator
31	Wai Sum Mong, Jianwen Zhu	A retargetable micro-architecture simulator.	DAC	2003	DBLP DOI BibTeX RDF
31	Edward Lank	A Retargetable Framework for Interactive Diagram Recognition.	ICDAR	2003	DBLP DOI BibTeX RDF
31	Guilan Dai, Jinlan Tian, Suqing Zhang, Weidu Jiang, Jun Dai	Retargetable cross compilation techniques: comparison and analysis of GCC and Zephyr.	ACM SIGPLAN Notices	2002	DBLP DOI BibTeX RDF	compiler infrastructures, zephyr, intermediate representations, GCC, machine descriptions, cross compilation
31	Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu	A Retargetable Embedded In-Circuit Emulation Module for Microprocessors.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
31	Frank Wolz, Reiner Kolla	A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
31	Nagisa Ishiura, Tatsuo Watanabe	Datapath oriented codesign method of application specific DSPs using retargetable compiler.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
31	Maghsoud Abbaspour, Jianwen Zhu	Retargetable binary utilities.	DAC	2002	DBLP DOI BibTeX RDF
31	Dmitri Boulytchev, Dmitry Lomov	An Empirical Study of Retargetable Compilers.	Ershov Memorial Conference	2001	DBLP DOI BibTeX RDF
31	Rajiv A. Ravindran, Rajat Moona	Retargetable Program Profiling Using High Level Processor Models.	HiPC	2001	DBLP DOI BibTeX RDF
31	Stefan Pees, Andreas Hoffmann 0002, Heinrich Meyr	Retargetable compiled simulation of embedded processors using a machine description language.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	HW/SW cosimulation, machine description languages, processor modeling and simulation, system-on-chip, instruction set simulators, compiled simulation, DSP processors
31	Subhash Chandra, Rajat Moona	Retargetable Functional Simulator Using High Level Processor Models.	VLSI Design	2000	DBLP DOI BibTeX RDF
31	Rainer Leupers, Peter Marwedel	Retargetable generation of code selectors from HDL processor models.	ED&TC	1997	DBLP DOI BibTeX RDF
31	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software.	Euro-Par	1997	DBLP DOI BibTeX RDF
31	Jack W. Davidson, Sanjay Jinturkar	Aggressive Loop Unrolling in a Retargetable Optimizing Compiler.	CC	1996	DBLP DOI BibTeX RDF	Code improving transformations, Compiler optimizations, Loop transformations, Loop unrolling
31	Dawson R. Engler	VCODE: a Retargetable, Extensible, Very Fast Dynamic Code Generation System.	PLDI	1996	DBLP DOI BibTeX RDF
31	Cristina Cifuentes, Vishv M. Malhotra	Binary Translation: Static, Dynamic, Retargetable?	ICSM	1996	DBLP DOI BibTeX RDF
31	Norman Ramsey, David R. Hanson	A Retargetable Debugger.	PLDI	1992	DBLP DOI BibTeX RDF	C, PostScript
31	Christopher W. Fraser	A retargetable compiler for ANSI C.	ACM SIGPLAN Notices	1991	DBLP DOI BibTeX RDF	C
31	Philip H. Sweany, Steven J. Beaty	Post-compaction register assignment in a retargetable compiler.	MICRO	1990	DBLP BibTeX RDF
31	Hartmut Feuerhahn	A data-flow driven resource allocation in a retargetable microcode compiler.	MICRO	1988	DBLP BibTeX RDF
31	Philip J. Hatcher, J. W. Tuller	Efficient retargetable compiler code generation.	ICCL	1988	DBLP DOI BibTeX RDF
31	Michael A. Howland, Robert A. Mueller, Philip H. Sweany	Trace scheduling optimization in a retargetable microcode compiler.	MICRO	1987	DBLP DOI BibTeX RDF
31	Lothar Nowak	Graph based retargetable microcode compilation in the MIMOLA design system.	MICRO	1987	DBLP DOI BibTeX RDF
31	Jack W. Davidson	A retargetable instruction reorganizer.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF
31	Vishv M. Malhotra, Sanjeev Kumar	Automatic Retargetable Code Generation: A New Technique.	FSTTCS	1986	DBLP DOI BibTeX RDF
24	Dmitri Boulytchev	BURS-Based Instruction Set Selection.	Ershov Memorial Conference	2006	DBLP DOI BibTeX RDF
24	Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun	C Compiler Retargeting Based on Instruction Semantics Models.	DATE	2005	DBLP DOI BibTeX RDF
24	Gunnar Braun, Achim Nohl, Andreas Hoffmann 0002, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr	A universal technique for fast and flexible instruction-set architecture simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
24	Jens Braunes, Steffen Köhler, Rainer G. Spallek	RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures.	ARCS	2004	DBLP DOI BibTeX RDF
24	Christoph W. Keßler, Andrzej Bednarski	Optimal integrated code generation for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection
24	Sungjoon Jung, Yunheung Paek	The very portable optimizer for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
24	Norman Ramsey, Mary F. Fernandez	Specifying Representations of Machine Instructions.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	encoding, decoding, compiler generation, relocation, object code, machine description, machine code
24	Jie Gong, Daniel D. Gajski, Alexandru Nicolau	Performance evaluation for application-specific architectures.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
24	Jack W. Davidson, David B. Whalley	Ease: An Environment for Architecture Study and Experimentation.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
20	Chao Wang 0003, Huizhen Zhang, Xuehai Zhou, Jinsong Ji, Aili Wang 0003	Tool Chain Support with Dynamic Profiling for RISP.	ISPA	2011	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, code mapping, retargetable compilation, dynamic profiling
20	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado	An open-source binary utility generator.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Platform debugging, retargetable tools, TLM
20	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
20	Prabhat Mishra 0001, Aviral Shrivastava, Nikil D. Dutt	Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation
20	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping