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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 516 publication records. Showing 516 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
59 | Issam Alzaher-Noufal, Michael Nicolaidis |
A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits |
53 | Michel Diaz, Guy Juanole, Jean-Pierre Courtiat |
Observer-A Concept for Formal On-Line Validation of Distributed Systems. |
IEEE Trans. Software Eng. |
1994 |
DBLP DOI BibTeX RDF |
observer concept, formal online validation, self-checking distributed systems design, erroneous behavior detection, observable output level, continuous checking, formal verified model, quasi-self-checking observers, industrial LAN, broadcast service, virtual ring MAC protocol testing, OSI layering management, open system architecture, run-time validation, Petri net based models, layered distributed architectures, formal verification, distributed processing, local area networks, transport protocols, performance measurements, open systems, access protocols, formal description techniques, transport layer, reference, link layer, online operation |
50 | Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis |
Totally Self Checking reconfigurable duplication system with separate internal fault indication. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication |
47 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
47 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
46 | Petros Oikonomakos, Mark Zwolinski |
On the Design of Self-Checking Controllers with Datapath Interactions. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
fault tolerance, Reliability, testing, automatic synthesis, error-checking, redundant design |
45 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
Design for Self-Checking and Self-Timed Datapath. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits |
44 | Michael Nicolaidis |
Efficient UBIST implementation for microprocessor sequencing parts. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits |
44 | Michael Nicolaidis |
Shorts in self-checking circuits. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
43 | Ilya Levin, Vladimir Sinelnikov |
Self-Checking of FPGA-Based Control Units. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
42 | José Manuel Cazeaux, Daniele Rossi 0001, Cecilia Metra |
Self-Checking Voter for High Speed TMR Systems. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
high reliabily, duplication and comparison, self-checking, voter, TMR systems |
42 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A Totally Self-Checking Dynamic Asynchronous Datapath. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider |
42 | Michael J. Liebelt, Cheng-Chew Lim |
A method for determining whether asynchronous circuits are self-checking. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise |
42 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. |
PRDC |
2000 |
DBLP DOI BibTeX RDF |
dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits |
42 | Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian |
Efficient Totally Self-Checking Shifter Design. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
parity prediction, fault-secure circuits, on-line testing, self-checking circuits |
39 | Petros Oikonomakos, Mark Zwolinski |
Foundation of Combined Datapath and Controller Self-checking Design. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Niraj K. Jha, Sying-Jyan Wang |
Design and synthesis of self-checking VLSI circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
39 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Ilana David, Ran Ginosar, Michael Yoeli |
Self-timed is self-checking. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
finite state machines, asynchronous systems, combinational logic, self-checkings, self-timed |
39 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Highly testable and compact single output comparator. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
comparators (circuits), single output comparator, self-checking n-input comparator, n-variable two-rail checker, equality checker, strongly code-disjoint, input code words, embedded comparators, VLSI, fault detection, totally-self-checking |
38 | Steven W. Burns, Niraj K. Jha |
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
parallel unordered coding scheme, parallel encoding/decoding, information symbols, checkbits, TSC checker, parallel algorithms, built-in self test, logic design, error detection codes, error-detecting codes, concurrent error detection, transient faults, unidirectional errors, totally self-checking checker, unordered codes, self-checking checker |
38 | Nikolaos Gaitanis |
Totally Self-Checking Checkers with Separate Internal Fault Indication. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
separate internal fault indication, functional circuit, two-element Boolean algebra, self-checking operator blocks, logic testing, fault location, fault, design technique, totally self-checking checkers, algebraic approach |
37 | Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky |
Synthesis of ASM-based Self-Checking Controllers. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
SSMM, fault tolerance, finite state machine, VHDL, signature analysis, self checking |
36 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults |
36 | Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal |
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
Concurrent checking, self–checking circuits, timing faults, very deep submicron, hardware fault tolerance, soft errors, defects, nanometer technologies |
36 | Vladimír Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois |
Thermal Monitoring of Self-Checking Systems. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
self-checking circuits, thermal testing, temperature sensors, thermal sensors |
36 | Donatella Sciuto, Cristina Silvano, Renato Stefanelli |
Systematic AUED Codes for Self-Checking Architectures. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
AUED Codes, Self-Checking Combinational Circuits, Stuck-at Faults, Unidirectional Errors |
36 | Michele Favalli, Cecilia Metra |
Low-level error recovery mechanism for self-checking sequential circuits. |
DFT |
1997 |
DBLP DOI BibTeX RDF |
low-level error recovery mechanism, self-checking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults |
34 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Niraj K. Jha |
A totally self-checking checker for Borden's code. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
33 | Steffen Tarnick |
Controllable self-checking checkers for conditional concurrent checking. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
33 | Stanislaw J. Piestrak |
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
TSC Berger code checker, Berger code, totally self-checking circuit, self-testing checker, two-rail code |
30 | Jerzy W. Greblicki, Jerzy Kotowski |
Automated Design of Totally Self-Checking Sequential Circuits. |
EUROCAST |
2009 |
DBLP DOI BibTeX RDF |
sequential circuits, Fault tolerant systems, totally self-checking circuits |
30 | Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin |
Survivable Self-Checking Sequential Circuits. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
self-checking sequential machines, survivable circuits, partially monotonous functions |
30 | Anzhela Yu. Matrosova, Sergey Ostanin |
Self-Checking FSM Design with Observing only FSM Outputs. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Self-checking design, unidirectional fault, PLA description, multilevel synthesis, FSM |
30 | Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri |
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Self-checking systems, Field Programmable Gate Arrays, Artificial neural networks, Space applications |
30 | Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee |
Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
Built-in intermediate voltage sensor, bridging fault, totally self-checking circuit |
30 | Shujian Zhang, Jon C. Muzio |
Evaluating the safety of self-checking circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
fail-safe evaluation, TSC, Markov model, self-checking circuit |
30 | Fadi Y. Busaba, Parag K. Lala |
A graph coloring based approach for self-checking logic circuit design. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault |
30 | Fadi Y. Busaba, Parag K. Lala |
Self-checking combinational circuit design for single and unidirectional multibit error. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
Input encoding, output encoding, unidirectional error, self-checking |
29 | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
Modified Stability Checking for On-line Error Detection. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection |
29 | Anna Antola, Vincenzo Piuri, Mariagiovanna Sami |
High-level Synthesis of Data Paths with Concurrent Error Detection. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
self-checking systems, high-level synthesis, concurrent error detection, data path |
28 | Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006 |
Design and Test of Self-checking Asynchronous Control Circuit. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Self Checking Reed Solomon Encoder. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Dilip P. Vasudevan, Parag K. Lala |
A Technique for Modular Design of Self-Checking Carry-Select Adder. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
28 | C. K. Tang, Parag K. Lala, James Patrick Parkerson |
A Technique for Designing Totally Self-Checking Domino Logic Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
28 | José Manuel Cazeaux, Daniele Rossi 0001, Cecilia Metra |
New High Speed CMOS Self-Checking Voter. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale |
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto |
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois |
Design of self-checking fully differential circuits and boards. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Michele Favalli, Cecilia Metra |
On the Design of Self-Checking Functional Units Based on Shannon Circuits. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Kanji Hirabayashi |
Self-checking CMOS circuits using pass-transistor logic. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
|
28 | David S. Rosenblum, Sriram Sankar, David C. Luckham |
Concurrent Runtime Checking of Annotated Ada Programs. |
FSTTCS |
1986 |
DBLP DOI BibTeX RDF |
|
27 | Daniel Etiemble |
Multivalued I2L Circuits for TSC Checkers. |
IEEE Trans. Computers |
1980 |
DBLP DOI BibTeX RDF |
totally self-checking comparator, multivalued logic, Error-detecting codes, totally self-checking checkers, I |
27 | Dhiraj K. Pradhan |
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design. |
IEEE Trans. Computers |
1978 |
DBLP DOI BibTeX RDF |
upper bound on the number of state variables, fault-secure networks, self-checking networks, single-transition-time assignments, unate next-state functions, unidirectional faults, universal assignments, fault detection, Asynchronous networks, Berger codes, self-checking checker |
27 | Alberto Bartoli, Giovanni Masarin |
On-line self-checking of replication consistency for autonomic computing. |
Clust. Comput. |
2006 |
DBLP DOI BibTeX RDF |
Fault detectors, Web services, Dependability, Availability, On-line testing, Self-check |
27 | Danny C. C. Ko, Melvin A. Breuer |
The design of self-checking multi-output combinational circuits. |
AFIPS National Computer Conference |
1977 |
DBLP DOI BibTeX RDF |
|
26 | Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami |
Semiconcurrent Error Detection in Data Paths. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
Semiconcurrent error detection, checking periodicity, resource minimization, fault tolerance, high-level synthesis, data flow graph, self-checking circuits |
26 | Anna Antola, Vincenzo Piuri, Mariagiovanna Sami |
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Semi-concurrent error detection, Fault tolerance, High-level synthesis, Data Flow Graphs, Self-checking circuits |
25 | Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky |
Self-checking sequential circuits with self-healing ability. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra |
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Error detecting codes, Transient faults, Self-checking circuits, Checker |
25 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Low Cost and High Speed Embedded Two-Rail Code Checker. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Self-checking circuits, checkers, error indicators, two-rail code |
25 | Michael Nicolaidis, Yervant Zorian |
On-Line Testing for VLSI - A Compendium of Approaches. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
fail-safe circuits, SEU hardened circuits, monitoring of reliability indicators, thermal monitors, radiation monitors, on-line testing, self-checking circuits, current monitors |
25 | Michele Favalli, Cecilia Metra |
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
bus based systems, on-line testing, two-rail checker |
25 | Michele Favalli, Cecilia Metra |
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Jerzy W. Greblicki, Stanislaw J. Piestrak |
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. |
EDCC |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis |
An SFS Berger check prediction ALU and its application to self-checking processor designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Wonhak Hong, Rajashekhar Modugu, Minsu Choi |
Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
Modulo 2^n+1 multiplier, arithmetic circuit design, compressor, online self-checking, international data encryption algorithm (IDEA), residue arithmetic |
25 | Wen-Feng Chang, Cheng-Wen Wu |
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
Fault tolerance, logic testing, on-line testing, totally-self-checking checker, m-out-of-n code |
25 | Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis |
Concurrent Delay Testing in Totally Self-Checking Systems. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators |
25 | Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis |
A Totally Self-Checking 1-out-of-3 Code Error Indicator. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
1-out-of-3 code, totally self checking circuits, error indicator |
25 | Jien-Chung Lo |
A Hyper Optimal Encoding Scheme for Self-Checking Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
logic circuit synthesis, output encoding, Concurrent error detection, self-checking circuits, unordered codes |
25 | D. A. Pierce, Parag K. Lala |
Modular implementation of efficient self-checking checkers for the Berger code. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
conventional Berger code, 1's counters, fully-testable circuits, partitioning, CMOS technology, totally self-checking checkers, Berger code |
25 | Steven S. Gorshe, Bella Bose |
A self-checking ALU design with efficient codes. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors |
25 | Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis |
An asynchronous totally self-checking two-rail code error indicator. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults |
25 | Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos |
Efficient Totally Self-Checking Checkers for a Class of Borden Codes. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
Borden codes, t-unidirectional error detecting (t-UED) codes, fault tolerant, fault detection, totally self-checking checker |
25 | Niraj K. Jha |
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers |
25 | T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo |
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
totally self-checking Berger code checker designs, generalized Berger code partitioning, m-out-of-n checker, error correction codes, error detection codes |
25 | Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram |
Design of Self-Checking Circuits Using DCVS Logic: A Case Study. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
DCVS logic, differential cascode voltage switch, low hardware-overhead costs, fault tolerance, fault tolerant computing, logic design, error detection, error correction, logic circuits, self-checking circuits |
25 | Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala |
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
1-out-of-N code, minimum gate delay, NOR array, NOR-NOR PLA, fault tolerant computing, logic testing, delays, logic design, translator, error detection codes, logic arrays, totally self-checking checker |
25 | Jien-Chung Lo, Suchai Thanawastien |
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
combinational totally self-checking 1-out-of-3 code checkers, NMOS, TSC goal, fault sequences, minimum fault sequences, MOS integrated circuits, logic testing, logic design, automatic testing, integrated logic circuits |
25 | Sudhir Dhawan, Ronald C. de Vries |
Design of Self-Checking Sequential Machines. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
error transmission, self-checking sequential machines, design, error detection, flip-flops, flip-flops, sequential machines, excitation, memory elements |
25 | Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou |
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
low-cost arithmetic codes, reliability, fault tolerant computing, partitioning, trees, error detection codes, totally self-checking checkers, gate levels |
25 | Sudhir Dhawan, Ronald C. de Vries |
Design of Self-Checking Iterative Networks. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
iterative network, iterated switching networks, redundancy, error detection, combinational circuit, error, combinatorial circuits, self-checking |
25 | Nikolaos Gaitanis |
Totally Self-Checking Checkers for Low-Cost Arithmetic Codes. |
IEEE Trans. Computers |
1985 |
DBLP DOI BibTeX RDF |
TSC residue generators, Inverse residue codes, low-cost codes, totally self-checking checkers |
25 | Petr Golan |
Design of Totally Self-Checking Checker for 1-out-of-3 Code. |
IEEE Trans. Computers |
1984 |
DBLP DOI BibTeX RDF |
fixed-weight codes, 1-out-of-3 code, TSC checkers, totally self-checking checkers, Constant weight codes, m-out-of-n codes |
25 | Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala |
Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) Codes. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
totally self-checking checkers, m-out-of-n codes |
25 | W. Kenneth Jenkins |
The Design of Error Checkers for Self-Checking Residue Number Arithmetic. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
Digital processors, self-checking arithmetic, fault tolerance, modular arithmetic, special purpose hardware, residue arithmetic |
25 | K. V. S. S. Prasad Rao, Dhruba Basu |
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
time domain redundancy, self-dual function, space domain redundancy, CMOS, multiple faults, self-checking circuits, combinatorial logic |
25 | James E. Smith 0001, Paklin Lam |
A Theory of Totally Self-Checking System Design. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
totally self-checking systems, Checker placement, detecting codes, self-testing, error propagation, fault secure |
25 | Javad Khakbaz |
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes. |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
code disjoint, 1-out-of-n code, programmable logic array (PLA) totally self-checking (TSC), Checker, two-rail code |
22 | Pavel Kubalík, Petr Fiser, Hana Kubátová |
Fault Tolerant System Design Method Based on Self-Checking Circuits. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Adam Matthews |
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld |
A Modulo p Checked Self-Checking Carry Select Adder. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cecilia Metra, Stefano Di Francescantonio, Martin Omaña 0001 |
Automatic Modification of Sequential Circuits for Self-Checking Implementation. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli |
Self-Checking Scheme for the On-Line Testing of Power Supply Noise. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Luca Schiano, Cecilia Metra, Diego Marino |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Luca Schiano, Cecilia Metra, Diego Marino |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Parag K. Lala, Alfred L. Burress |
A technique for designing self-checking logic for FPGAs. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
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