Search results for "self-resetting"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
92	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
92	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
58	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Self-Resetting Latches for Asynchronous Micro-Pipelines.	DAC	2007	DBLP DOI BibTeX RDF
58	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
58	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
41	Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Self-Resetting Stage Logic Pipelines.	ISVLSI	2005	DBLP DOI BibTeX RDF
41	Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi	High-speed add-compare-select units using locally self-resetting CMOS.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
41	Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman	A robust self-resetting CMOS 32-bit parallel adder.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
41	Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer	Static timing analysis for self resetting circuits.	ICCAD	1996	DBLP DOI BibTeX RDF
34	Abdelhalim Alsharqawi, Abdel Ejnioui	Clockless Pipelining for Coarse Grain Datapaths.	VLSI Design	2006	DBLP DOI BibTeX RDF
34	G. Privitera, Francesco Pessolano	Analysis of High-Speed Logic Families.	PATMOS	2003	DBLP DOI BibTeX RDF
34	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee	Verification of Delayed-Reset Domino Circuits Using ATACS.	ASYNC	1999	DBLP DOI BibTeX RDF
24	Wanlong Zhao, Yuejun Zhang, Mingze Ren, Liang Wen, Pengjun Wang	A 7nm-Based Decodable Self-Resetting Regfile Circuit.	ASICON	2023	DBLP DOI BibTeX RDF
24	Ehad Akeila, Zoran Salcic, Akshya Swain	Reducing Low-Cost INS Error Accumulation in Distance Estimation Using Self-Resetting.	IEEE Trans. Instrum. Meas.	2014	DBLP DOI BibTeX RDF
24	Sunghyun Park 0002, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan	40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.	DATE	2013	DBLP DOI BibTeX RDF
24	Joo-Seong Kim, Bai-Sun Kong	Self-Resetting Level-Conversion Flip-Flops with Direct Output Feedback for Dual-Supply SoCs.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
24	Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel	Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	Wei Hwang, Rajiv V. Joshi, Walter H. Henkels	A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	Kenneth Y. Yun, Ayoob E. Dooply	Optimal Evaluation Clocking of Self-Resetting Domino Pipelines.	ASP-DAC	1999	DBLP DOI BibTeX RDF
17	Timothy G. Constandinou, Julius Georgiou, Chris Toumazou	A micropower front-end interface for differential-capacitive sensor systems.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Suwen Yang, Mark R. Greenstreet	Simulating Improbable Events.	DAC	2007	DBLP DOI BibTeX RDF
17	Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Pipelined SRSL Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Xiaohua Kong, Radu Negulescu	Bolstering Faith in GasP Circuits through Formal Verification.	ASYNC	2004	DBLP DOI BibTeX RDF
17	Peter A. Beerel, Ken S. Stevens, Hoshik Kim	Relative Timing Based Verification of Timed Circuits and Systems.	ASYNC	2002	DBLP DOI BibTeX RDF	Relative Timing, Verification and Timed Circuits, Timing Constraints
17	Ivan E. Sutherland, Scott Fairbanks	GasP: A Minimal FIFO Control.	ASYNC	2001	DBLP DOI BibTeX RDF
17	Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng 0001	Timed circuits: a new paradigm for high-speed design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Tero Säntti, Jouni Isoaho	Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
17	Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann	Design Of Provably Correct Storage Arrays.	VLSI Design	2001	DBLP DOI BibTeX RDF
17	Rajiv V. Joshi, Wei Hwang	Design Considerations and Implementation of a High Performance Dynamic Register File.	VLSI Design	1999	DBLP DOI BibTeX RDF