Search results for "self-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
63	Joan Carletta, Christos A. Papachristou	Structural constraints for circular self-test paths.	VTS	1995	DBLP DOI BibTeX RDF	circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
59	Oliver F. Haberl, Thomas Kropf	HIST: A hierarchical self test methodology for chips, boards, and systems.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Boundary-scan architecture, hierarchical self test, self test synthesis, built-in self test (BIST), system test
58	Lahouari Sebaa, Norm Gardner, Robert Neidorff, Rich Valley	Self-test in a VCM driver chip.	VTS	1995	DBLP DOI BibTeX RDF	driver circuits, bridge circuits, digital-analogue conversion, pulse amplifiers, VCM driver chip, self-test mode, complex mixed-signal device, device under test, voice-coil motor, H-bridge amplifier, onchip D/A converter, self-test circuitry, 11 bit, built-in self test, integrated circuit testing, design for testability, mixed analogue-digital integrated circuits, instrumentation amplifiers
57	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
55	Xiaoliang Bai, Sujit Dey, Janusz Rajski	Self-test methodology for at-speed test of crosstalk in chip interconnects.	DAC	2000	DBLP DOI BibTeX RDF
54	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
52	Abhijit Chatterjee, Jacob A. Abraham	Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
49	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A built-in self-test and self-diagnosis scheme for embedded SRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
48	Li Chen, Srivaths Ravi 0001, Anand Raghunathan, Sujit Dey	A scalable software-based self-test methodology for programmable processors.	DAC	2003	DBLP DOI BibTeX RDF	scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test
48	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
46	Li Chen, Sujit Dey	Software-based self-testing methodology for processor cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
46	Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng	Embedded hardware and software self-testing methodologies for processor cores.	DAC	2000	DBLP DOI BibTeX RDF
43	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	ETS	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
42	Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois	Generation of Electrically Induced Stimuli for MEMS Self-Test.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	MEMS test case-studies, MEMS failure mechanisms, BIST, self-test
41	Ugur Kalay, Douglas V. Hall, Marek A. Perkowski	A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
40	Sying-Jyan Wang, Chen-Jung Wei	Efficient built-in self-test algorithm for memory.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
40	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
40	Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi	Low-cost DC built-in self-test of linear analog circuits using checksums.	VLSI Design	1996	DBLP DOI BibTeX RDF	DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
40	Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
39	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for faults in system backplanes.	ICCAD	1997	DBLP DOI BibTeX RDF	BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration
39	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
39	Nilanjan Mukherjee, Ramesh Karri	Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
38	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
38	Arno Kunzmann, Frank Böhland	Self-test of sequential circuits with deterministic test pattern sequences.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Deterministic Test Pattern Sequences, Field-Programmable Gate-Arrays (FPGAs), Design-for-Testability, Sequential Circuits, Automatic Test Pattern Generation (ATPG), Self-Test
37	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
37	Albrecht P. Stroele	Signature analysis and aliasing for sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
37	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
37	Albrecht P. Stroele, Frank Mayer	Methods to reduce test application time for accumulator-based self-test.	VTS	1997	DBLP DOI BibTeX RDF	accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation
37	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
37	Yervant Zorian, Hakim Bederr	An Effective Multi-Chip BIST Scheme.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, DFT, MCM testing
36	K. Y. Ko, Mike W. T. Wong	New built-in self-test technique based on addition/subtraction of selected node voltages.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	node voltages, built-in self test, built-in self-test, fault detection, fault location, analogue circuits
36	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
35	Dimitris Gizopoulos	Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
35	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	A Self Test Program Design Technique for Embedded DSP Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	self test programs, pseudorandom BIST, LSFR, DSP, ATPG
35	Li Chen, Sujit Dey	DEFUSE: A Deterministic Functional Self-Test Methodology for Processors.	VTS	2000	DBLP DOI BibTeX RDF	microprocessor, self-test, instructions, structural testing, At-speed testing
35	Jian Shen, Jacob A. Abraham	Synthesis of Native Mode Self-Test Programs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	native mode self-test, test synthesis, functional test generation
34	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.	DFT	2004	DBLP DOI BibTeX RDF
34	Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001	Systematic software-based self-test for pipelined processors.	DAC	2006	DBLP DOI BibTeX RDF	functional testing, software-based self-test, processor testing
34	Michael Nicolaidis	Self-exercising checkers for unified built-in self-test (UBIST).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
34	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
34	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid software-based self-testing methodology for embedded processor.	SAC	2008	DBLP DOI BibTeX RDF	embedded processor testing, fault coverage, functional testing, software-based self-test
34	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis	A concurrent built-in self-test architecture based on a self-testing RAM.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
34	V. Loukusa	Embedded System Level Self-Test for Mixed-Signal IO Verification.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	IO connectivity, DFT, histogram, testability, self-test, mixed-signal, system level
33	Kewal K. Saluja	On-chip testing of random access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
33	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
33	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre	AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis.	DELTA	2008	DBLP DOI BibTeX RDF	AES core, BIST, secure systems
32	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
32	R. K. Sharma, Aditi Sood	Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Faults.	ICSAP	2010	DBLP DOI BibTeX RDF	Defect-Per Million (DPM), Memory Built-in Self Test (MBIST), Microcoded MBIST, MUT (Memory Under Test), Built-In Self Test (BIST)
32	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
32	Peter D. Hortensius, Robert D. McLeod, Howard C. Card	Cellular Automata-Based Signature analysis for Built-in Self-Test.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	signature analysis properties, one-dimensional cellular automata, cyclic-group rules, CALBO, cellular automata-based logic block observation, BILBO, built-in block observation, logic testing, built-in self-test, built-in self test, LFSR, linear feedback shift register, finite automata, test pattern generation
32	Bernhard Eschermann	An implicitly testable boundary scan TAP controller.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	test controller, BIST, self-test, boundary scan, synthesis for testability, controller design
31	Christian Dufaza	Multiple Paths Sensitization of Digital Oscillation Built-In Self Test.	ICCD	1999	DBLP DOI BibTeX RDF	DOBIST, Test, Built-In Self Test
31	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
31	Andrzej Krasniewski, Slawomir Pilarski	Circular self-test path: a low-cost BIST technique for VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
31	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
31	Jacob Savir	On shrinking wide compressors.	VTS	1995	DBLP DOI BibTeX RDF	wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
31	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
31	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
31	C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra	A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
30	Li Chen, Xiaoliang Bai, Sujit Dey	Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	interconnect, crosstalk, processor, self-test
30	Markus Seuring	Combining Scan Test and Built-in Self Test.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MBIST, BIST, scan test, production test, stress test
30	Yanjing Li, Samy Makar, Subhasish Mitra	CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns.	DATE	2008	DBLP DOI BibTeX RDF
29	Sungbae Hwang, Jacob A. Abraham	Selective-run built-in self-test using an embedded processor.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator
29	Paul Chang, Brion L. Keller, Sarala Paliwal	Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm.	ICCD	1999	DBLP DOI BibTeX RDF	LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation
29	Albrecht P. Stroele	Arithmetic Pattern Generators for Built-In Self-Test.	ICCD	1996	DBLP DOI BibTeX RDF	Arithmetic functions, built-in self-test, design for testability, pattern generator
29	Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama	Built-in self test for C-testable ILA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi	Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing
29	Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi	Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.	VTS	1997	DBLP DOI BibTeX RDF	digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
29	T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael	Faulty chip identification in a multi chip module system.	VTS	1996	DBLP DOI BibTeX RDF	faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
29	Manoj Franklin	Fast computation of C-MISR signatures.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
29	Joan Carletta, Christos A. Papachristou	Testability analysis and insertion for RTL circuits based on pseudorandom BIST.	ICCD	1995	DBLP DOI BibTeX RDF	pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
29	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
29	S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
29	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
29	Andrzej Krasniewski, Slawomir Pilarski	Circular Self-Test Path: A Low-Cost BIST Technique.	DAC	1987	DBLP DOI BibTeX RDF
28	René Kothe, Christian Galke, Heinrich Theodor Vierhaus	A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features.	IOLTS	2005	DBLP DOI BibTeX RDF
28	Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	A constraint-based solution for on-line testing of processors embedded in real-time applications.	SBCCI	2005	DBLP DOI BibTeX RDF	test space exploration, real-time systems, embedded processors, on-line testing, software-based self-test
28	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	mutual checking, multiple signature testing, self loops, built-in self test, aliasing
28	Albrecht P. Stroele, Hans-Joachim Wunderlich	Test register insertion with minimum hardware cost.	ICCAD	1995	DBLP DOI BibTeX RDF	test register insertion, BILBO, CBILBO, Built-in self-test
28	Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu	Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
28	Wimol San-Um, Masayoshi Tachibana	Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
28	Jiang Shi, Ricky Smith	Built-In Self-Test for Embedded Voltage Regulator.	DELTA	2008	DBLP DOI BibTeX RDF	voltage output, current loading, built-in, embedded, manufacturing, regulator, self-test
28	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
28	Mohammad Tehranipoor, Reza M. Rad	Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Lei Li 0036, Zhanglei Wang, Krishnendu Chakrabarty	Scan-BIST based on cluster analysis and the encoding of repeating sequences.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	clustering test data volume, Built-in self-test (BIST), test compression
27	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
27	George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis	Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores.	IOLTS	2003	DBLP DOI BibTeX RDF
27	Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois	Electrically Induced Stimuli For MEMS Self-Test.	VTS	2001	DBLP DOI BibTeX RDF
27	Wei Zhao, Christos A. Papachristou	Testing DSP Cores Based on Self-Test Programs.	DATE	1998	DBLP DOI BibTeX RDF
26	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
26	Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar	Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems.	SIES	2007	DBLP DOI BibTeX RDF
26	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test
26	Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy	Built In Self Test for Ring Addressed FIFOs with Transparent Latches.	MTDT	1999	DBLP DOI BibTeX RDF	Built In Self Test, Memory testing, Embedded memories
26	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An efficient built-in self test method for robust path delay fault testing.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
26	Saman Adham, Sanjay Gupta	DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
26	Antonis M. Paschalis, Dimitris Gizopoulos	Effective software-based self-test strategies for on-line periodic testing of embedded processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Antonis M. Paschalis, Dimitris Gizopoulos	Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors.	DATE	2004	DBLP DOI BibTeX RDF
26	Uthman Alsaiari, Resve A. Saleh	Testable and self-repairable structured logic design.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
26	Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara	BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test