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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 319 occurrences of 199 keywords
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Results
Found 437 publication records. Showing 437 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
119 | R. S. Hogg, W. I. Hughes, David W. Lloyd |
A Novel Asynchronous ALU for Massively Parallel Architectures. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit |
99 | William F. Richardson, Erik Brunvand |
Precise exception handling for a self-timed processor. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems |
81 | T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas |
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
self-timed CMOS design, testing interconnections, boundary-scan, MCM testing |
72 | Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha |
Improving self-timed pipeline ring performance through the addition of buffer loops. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing |
68 | Mark R. Greenstreet |
Implementing a STARI chip. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits |
67 | Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang |
A self-timed redundant-binary number to binary number converter for digital arithmetic processors. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems |
67 | Ilana David, Ran Ginosar, Michael Yoeli |
Self-timed is self-checking. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
finite state machines, asynchronous systems, combinational logic, self-checkings, self-timed |
65 | Antonio J. Acosta 0001, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas |
New CMOS VLSI linear self-timed architectures. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources |
65 | Sandeep Pagey, Ajay Khoche, Erik Brunvand |
DFT for fast testing of self-timed control circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software |
64 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald |
Self-Timed Carry-Lookahead Adders. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders |
64 | Z. C. Yu, Stephen B. Furber, Luis A. Plana |
An Investigation into the Security of Self-Timed Circuits. |
ASYNC |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Mark R. Greenstreet, Brian de Alwis |
How to Achieve Worst-Case Performance. |
ASYNC |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Sundararajan Sriram, Edward A. Lee |
Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. |
J. VLSI Signal Process. |
1997 |
DBLP DOI BibTeX RDF |
|
57 | Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet |
Verifying a Self-Timed Divider. |
ASYNC |
1998 |
DBLP DOI BibTeX RDF |
model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence |
56 | Peggy B. K. Pang, Mark R. Greenstreet |
Self-Timed Meshes Are Faster Than Synchronous. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD |
55 | Ted E. Williams |
Performance of iterative computation in self-timed rings. |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
53 | Anthony Winstanley, Mark R. Greenstreet |
Temporal Properties of Self-Timed Rings. |
CHARME |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak |
Design of Self-Synchronized Component FSMs for Self-Timed Systems. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
50 | Ajay Khoche, Erik Brunvand |
Testing self-timed circuits using partial scan. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits |
50 | Ajay Khoche, Erik Brunvand |
A partial scan methodology for testing self-timed circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits |
48 | Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering |
Self timed division and square-root extraction. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks |
48 | Erik Brunvand |
Low latency self-timed flow-through FIFOs. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
self-timed flow-through FIFO, linear flow-through FIFO, parallel FIFO, tree FIFO, square FIFO, folded FIFO, low latency type, field programmable gate arrays, VLSI, asynchronous circuits, CMOS logic circuits |
47 | Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald 0001, Tong Zhang 0002 |
Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Scott C. Smith |
Speedup of Self-Timed Digital Systems Using Early Completion. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
asynchronous, NCL, NULL Convention Logic, delay-insensitive |
47 | Erik Brunvand |
Designing self-timed systems using concurrent programs. |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
47 | Erik Brunvand |
Using FPGAs to implement self-timed systems. |
J. VLSI Signal Process. |
1993 |
DBLP DOI BibTeX RDF |
|
39 | Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah |
Self-timed circuits for energy harvesting AC power supplies. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory |
39 | Jung-Lin Yang, Erik Brunvand |
Using dynamic domino circuits in self-timed systems. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
asynchronous circuits, domino logic, self-timed circuits |
39 | Frank Grassert, Dirk Timmermann |
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
redundant numbers, self-timed logic, single-rail logic, low power, dynamic logic |
39 | Jae-Hee Won, Kiyoung Choi |
Low power self-timed Radix-2 division (poster session). |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
RSD, radix-2 division, low power, self-timed |
39 | Mark A. Franklin, Prithvi Prabhu |
Performance Optimization of Self-Timed Circuits. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
completion detection, hybrid completion method, Asynchronous, self-timed |
39 | Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto |
30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
simulation, CMOS, division, square root, self-timed, SRT, on-the-fly |
39 | Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda |
Measurement of power supply noise tolerance of self-timed processor. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Syed Rafay Hasan, Yvon Savaria |
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Yuan Chen 0002, Fei Xia, Alexandre Yakovlev |
Virtual self-timed blocks for systems-on-chip. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Frank te Beest, Ad M. G. Peeters |
A Multiplexor Based Test Method for Self-Timed Circuits. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Kip C. Killpack, Eric Mercer, Chris J. Myers |
A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Seokjin Kim, Ramalingam Sridhar |
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
39 | Lars Skovby Nielsen, Cees Niessen, Jens Sparsø, Kees van Berkel 0001 |
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson |
Mitigating static power in current-sensed interconnects. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
interconnect circuits, static power, self-timed systems |
34 | Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier |
An Event Spacing Experiment. |
ASYNC |
2002 |
DBLP DOI BibTeX RDF |
Charlie Diagrams, self-timed rings, timing analysis, phase transitions, attractors, hysteresis |
34 | Eric Senn, Bertrand Y. Zavidovique |
Examples of Image Processing to Benefit from an Asynchronous Implementation. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
asynchronous implementation, machine architecture, router circuit, self-timed design, image processing, image processing, VLSI implementation, communication performances, salient features |
33 | Li-Kai Chang, Fu-Chiung Cheng |
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
Quantum Boolean circuits, Sequentialn circuits, State graph, Synthesis, Asynchronous circuits |
33 | Kenneth Y. Yun, Kevin W. James, Robert H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz |
A self-timed real-time sorting network. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
33 | R. S. Hogg, David W. Lloyd, W. I. Hughes |
Self-Timed Communication Strategies for Massively Parallel Systolic Architectures. |
CONPAR |
1994 |
DBLP DOI BibTeX RDF |
Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial |
32 | Jürgen Teich, Lothar Thiele, Edward A. Lee |
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Ptolemy design system, deterministic discrete event model, heterogeneous real-time systems, mixed asynchronous/synchronous systems, schedule constraints, synchronously clocked systems, timed marked graphs, simulation, modeling, real-time systems, discrete event simulation, timing analysis, finite buffering, self-timed systems |
31 | Gensoh Matsubara, Nobuhiro Ide |
A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
floating point, division, square root, self-timed |
31 | Seokjin Kim, Ramalingam Sridhar |
A local clocking approach for self-timed datapath designs. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits |
31 | Ilana David, Ran Ginosar, Michael Yoeli |
An Efficient Implementation of Boolean Functions as Self-Timed Circuits. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
logic module, temporal logic, temporal logic, Boolean functions, Boolean functions, logic design, correctness, logic circuits, automatic synthesis, formal proof, self-timed circuits, functional constraints |
31 | Ilana David, Ran Ginosar, Michael Yoeli |
Implementing Sequential Machines as Self-Timed Circuits. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
temporal behaviour constraints, master-slave register, state table, finite state machine, logic design, finite automata, sequential machines, combinational logic, combinatorial mathematics, self-timed circuits, automatic compiler |
30 | P. Balasubramanian 0001, David A. Edwards, Charlie Brej |
Self-timed full adder designs based on hybrid input encoding. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila |
Self-timed thermal sensing and monitoring of multicore systems. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Tadashi Kunieda, Teijiro Isokawa, Ferdinand Peper, Ayumu Saitoh, Naotake Kamiura, Nobuyuki Matsui |
Reconfiguring Circuits Around Defects in Self-Timed Cellular Automata. |
ACRI |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Niklas Lotze, Maurits Ortmanns, Yiannos Manoli |
A Study on self-timed asynchronous subthreshold logic. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin |
High-Level Synthesis for Self-Timed Systems. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere |
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications. |
PDCAT |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Vassilis Zebilis, Christos P. Sotiriou |
Controlling Event Spacing in Self-Timed Rings. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng |
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov |
Design and Analysis of a Self-Timed Duplex Communication System. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
30 | W. J. Bainbridge, Luis A. Plana, Stephen B. Furber |
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Jung-Lin Yang, Erik Brunvand |
Self-Timed Design with Dynamic Domino Circuits. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Harri Lampinen, Pauli Perälä, Olli Vainio |
Design of a self-timed asynchronous parallel FIR filter using CSCD. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Albert Koelmans, D. J. Kinniment |
Asynchronous Communication Mechanisms Using Self-Timed Circuits. |
ASYNC |
2000 |
DBLP DOI BibTeX RDF |
|
30 | George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001 |
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. |
ASYNC |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Märt Saarepera, Tomohiro Yoneda |
A Self-Timed Implementation of Boolean Functions. |
ASYNC |
1999 |
DBLP DOI BibTeX RDF |
|
30 | KiJong Lee, Kiyoung Choi |
Self-timed divider based on RSD number system. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Mark E. Dean, David L. Dill, Mark Horowitz |
Self-timed logic using Current-Sensing Completion Detection (CSCD). |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Michael Kishinevsky, Alex Kondratyev, Alexander Taubin |
Specification and analysis of self-timed circuits. |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Padmanabhan Balasubramanian |
Self-Timed Logic and the Design of Self-Timed Adders. |
|
2010 |
RDF |
|
26 | Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens |
Modeling and Verifying Circuits Using Generalized Relative Timing. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert |
A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
dummy bitline driver, self-timed memory, low power, SRAM, statistical design |
26 | Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang |
A GALS Infrastructure for a Massively Parallel Multiprocessor. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling |
26 | Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou |
Circuits for energy harvesting sensor signal processing. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory |
26 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver |
A Coarse-Grain Phased Logic CPU. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines |
26 | Mukul Khandelia, Shuvra S. Bhattacharyya |
Contention-Conscious Transaction Ordering in Embedded Multiprocessors. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
self-timed scheduling, multiprocessor synchronization, interprocessor communication, dataflow programming, embedded multiprocessors |
26 | Ajay Khoche, Erik Brunvand |
Critical hazard free test generation for asynchronous circuits. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm |
26 | Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee |
Latency-constrained Resynchronization for Multiprocessor DSP Implementation. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
static multi-processor schedules, iterative dataflow programs, self-timed execution, latency, synchronization overhead |
26 | Sandeep Pagey |
Fast functional testing of delay-insensitive circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates |
26 | Bret Stott, Dave Johnson 0003, Venkatesh Akella |
Asynchronous 2-D discrete cosine transform core processor. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron |
25 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger |
Early evaluation for performance enhancement in phased logic. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Harri Lampinen, Olli Vainio |
Current-sensing completion detection method for standard cell based digital system design. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno |
Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. |
ASYNC |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee |
Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. |
ASAP |
1995 |
DBLP DOI BibTeX RDF |
multiprocessor implementation, synchronization, dataflow, static scheduling, iterative computation |
24 | Leonid Ya. Rosenblum, Alexandre Yakovlev |
Signal Graphs: From Self-Timed to Timed Ones. |
PNPM |
1985 |
DBLP BibTeX RDF |
|
22 | Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester |
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal |
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Raphael Berner, Patrick Lichtsteiner, Tobi Delbrück |
Self-timed vertacolor dichromatic vision sensor for low power pattern detection. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Fu-Chiung Cheng, Shu-Ming Chang, Chi-Huam Shieh |
Detection and Generation of Self-Timed Pipelines from High Level Specifications. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Gennette Gill, John Hansen, Montek Singh |
Loop pipelining for high-throughput stream computation using self-timed rings. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Scott Fairbanks, Simon W. Moore |
Self-Timed Circuitry for Global Clocking. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Yousuke Takada, Teijiro Isokawa, Ferdinand Peper, Nobuyuki Matsui |
Universal Construction on Self-Timed Cellular Automata. |
ACRI |
2004 |
DBLP DOI BibTeX RDF |
|
22 | W. Kuang, J. S. Yuan, Abdel Ejnioui |
Supply Voltage Scalable System Design Using Self-Timed Circuits. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner |
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. |
ASYNC |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ajanta Chakraborty, Mark R. Greenstreet |
Efficient Self-Timed Interfaces for Crossing Clock Domains. |
ASYNC |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Shuji Sannomiya, Yoichi Omori, Makoto Iwata |
A Macroscopic Behavior Model for Self-Timed Pipeline Systems. |
PADS |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Christophe Bobda |
A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
|
22 | W. Kuang, J. S. Yuan |
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver |
Generalized Early Evaluation in Self-Timed Circuits. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Martin Feldhofer, Thomas Trathnigg, Bernd Schnitzer |
A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
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