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Searching for phrase self-timed (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1982-1991 (21) 1992-1994 (26) 1995 (23) 1996-1997 (21) 1998 (15) 1999 (16) 2000 (24) 2001-2002 (28) 2003 (28) 2004 (16) 2005 (24) 2006 (16) 2007 (20) 2008-2009 (24) 2010 (17) 2011-2012 (17) 2013-2014 (19) 2015-2016 (28) 2017-2018 (16) 2019-2020 (15) 2021-2022 (16) 2023 (7)
Publication types (Num. hits)
article(117) inproceedings(316) phdthesis(4)
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Found 437 publication records. Showing 437 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
119R. S. Hogg, W. I. Hughes, David W. Lloyd A Novel Asynchronous ALU for Massively Parallel Architectures. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
99William F. Richardson, Erik Brunvand Precise exception handling for a self-timed processor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
81T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
72Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha Improving self-timed pipeline ring performance through the addition of buffer loops. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing
68Mark R. Greenstreet Implementing a STARI chip. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits
67Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang A self-timed redundant-binary number to binary number converter for digital arithmetic processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
67Ilana David, Ran Ginosar, Michael Yoeli Self-timed is self-checking. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF finite state machines, asynchronous systems, combinational logic, self-checkings, self-timed
65Antonio J. Acosta 0001, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas New CMOS VLSI linear self-timed architectures. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
65Sandeep Pagey, Ajay Khoche, Erik Brunvand DFT for fast testing of self-timed control circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software
64Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald Self-Timed Carry-Lookahead Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
64Z. C. Yu, Stephen B. Furber, Luis A. Plana An Investigation into the Security of Self-Timed Circuits. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
58Mark R. Greenstreet, Brian de Alwis How to Achieve Worst-Case Performance. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
58Sundararajan Sriram, Edward A. Lee Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
57Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet Verifying a Self-Timed Divider. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
56Peggy B. K. Pang, Mark R. Greenstreet Self-Timed Meshes Are Faster Than Synchronous. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD
55Ted E. Williams Performance of iterative computation in self-timed rings. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
53Anthony Winstanley, Mark R. Greenstreet Temporal Properties of Self-Timed Rings. Search on Bibsonomy CHARME The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak Design of Self-Synchronized Component FSMs for Self-Timed Systems. Search on Bibsonomy EUROMICRO The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
50Ajay Khoche, Erik Brunvand Testing self-timed circuits using partial scan. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
50Ajay Khoche, Erik Brunvand A partial scan methodology for testing self-timed circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
48Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering Self timed division and square-root extraction. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks
48Erik Brunvand Low latency self-timed flow-through FIFOs. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF self-timed flow-through FIFO, linear flow-through FIFO, parallel FIFO, tree FIFO, square FIFO, folded FIFO, low latency type, field programmable gate arrays, VLSI, asynchronous circuits, CMOS logic circuits
47Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald 0001, Tong Zhang 0002 Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Scott C. Smith Speedup of Self-Timed Digital Systems Using Early Completion. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF asynchronous, NCL, NULL Convention Logic, delay-insensitive
47Erik Brunvand Designing self-timed systems using concurrent programs. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
47Erik Brunvand Using FPGAs to implement self-timed systems. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
39Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah Self-timed circuits for energy harvesting AC power supplies. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory
39Jung-Lin Yang, Erik Brunvand Using dynamic domino circuits in self-timed systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF asynchronous circuits, domino logic, self-timed circuits
39Frank Grassert, Dirk Timmermann Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF redundant numbers, self-timed logic, single-rail logic, low power, dynamic logic
39Jae-Hee Won, Kiyoung Choi Low power self-timed Radix-2 division (poster session). Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RSD, radix-2 division, low power, self-timed
39Mark A. Franklin, Prithvi Prabhu Performance Optimization of Self-Timed Circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF completion detection, hybrid completion method, Asynchronous, self-timed
39Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto 30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF simulation, CMOS, division, square root, self-timed, SRT, on-the-fly
39Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda Measurement of power supply noise tolerance of self-timed processor. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Syed Rafay Hasan, Yvon Savaria Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Yuan Chen 0002, Fei Xia, Alexandre Yakovlev Virtual self-timed blocks for systems-on-chip. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Frank te Beest, Ad M. G. Peeters A Multiplexor Based Test Method for Self-Timed Circuits. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Kip C. Killpack, Eric Mercer, Chris J. Myers A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. Search on Bibsonomy ARVLSI The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Seokjin Kim, Ramalingam Sridhar Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
39Lars Skovby Nielsen, Cees Niessen, Jens Sparsø, Kees van Berkel 0001 Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
34Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson Mitigating static power in current-sensed interconnects. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect circuits, static power, self-timed systems
34Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier An Event Spacing Experiment. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Charlie Diagrams, self-timed rings, timing analysis, phase transitions, attractors, hysteresis
34Eric Senn, Bertrand Y. Zavidovique Examples of Image Processing to Benefit from an Asynchronous Implementation. Search on Bibsonomy CAMP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF asynchronous implementation, machine architecture, router circuit, self-timed design, image processing, image processing, VLSI implementation, communication performances, salient features
33Li-Kai Chang, Fu-Chiung Cheng Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Quantum Boolean circuits, Sequentialn circuits, State graph, Synthesis, Asynchronous circuits
33Kenneth Y. Yun, Kevin W. James, Robert H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz A self-timed real-time sorting network. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33R. S. Hogg, David W. Lloyd, W. I. Hughes Self-Timed Communication Strategies for Massively Parallel Systolic Architectures. Search on Bibsonomy CONPAR The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial
32Jürgen Teich, Lothar Thiele, Edward A. Lee Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Ptolemy design system, deterministic discrete event model, heterogeneous real-time systems, mixed asynchronous/synchronous systems, schedule constraints, synchronously clocked systems, timed marked graphs, simulation, modeling, real-time systems, discrete event simulation, timing analysis, finite buffering, self-timed systems
31Gensoh Matsubara, Nobuhiro Ide A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF floating point, division, square root, self-timed
31Seokjin Kim, Ramalingam Sridhar A local clocking approach for self-timed datapath designs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
31Ilana David, Ran Ginosar, Michael Yoeli An Efficient Implementation of Boolean Functions as Self-Timed Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF logic module, temporal logic, temporal logic, Boolean functions, Boolean functions, logic design, correctness, logic circuits, automatic synthesis, formal proof, self-timed circuits, functional constraints
31Ilana David, Ran Ginosar, Michael Yoeli Implementing Sequential Machines as Self-Timed Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF temporal behaviour constraints, master-slave register, state table, finite state machine, logic design, finite automata, sequential machines, combinational logic, combinatorial mathematics, self-timed circuits, automatic compiler
30P. Balasubramanian 0001, David A. Edwards, Charlie Brej Self-timed full adder designs based on hybrid input encoding. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
30Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila Self-timed thermal sensing and monitoring of multicore systems. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
30Tadashi Kunieda, Teijiro Isokawa, Ferdinand Peper, Ayumu Saitoh, Naotake Kamiura, Nobuyuki Matsui Reconfiguring Circuits Around Defects in Self-Timed Cellular Automata. Search on Bibsonomy ACRI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Niklas Lotze, Maurits Ortmanns, Yiannos Manoli A Study on self-timed asynchronous subthreshold logic. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin High-Level Synthesis for Self-Timed Systems. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications. Search on Bibsonomy PDCAT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Vassilis Zebilis, Christos P. Sotiriou Controlling Event Spacing in Self-Timed Rings. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov Design and Analysis of a Self-Timed Duplex Communication System. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30W. J. Bainbridge, Luis A. Plana, Stephen B. Furber The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Jung-Lin Yang, Erik Brunvand Self-Timed Design with Dynamic Domino Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Harri Lampinen, Pauli Perälä, Olli Vainio Design of a self-timed asynchronous parallel FIR filter using CSCD. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
30Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Albert Koelmans, D. J. Kinniment Asynchronous Communication Mechanisms Using Self-Timed Circuits. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
30George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001 An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
30Märt Saarepera, Tomohiro Yoneda A Self-Timed Implementation of Boolean Functions. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
30KiJong Lee, Kiyoung Choi Self-timed divider based on RSD number system. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
30Mark E. Dean, David L. Dill, Mark Horowitz Self-timed logic using Current-Sensing Completion Detection (CSCD). Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
30Michael Kishinevsky, Alex Kondratyev, Alexander Taubin Specification and analysis of self-timed circuits. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
27Padmanabhan Balasubramanian Self-Timed Logic and the Design of Self-Timed Adders. Search on Bibsonomy 2010   RDF
26Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens Modeling and Verifying Circuits Using Generalized Relative Timing. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dummy bitline driver, self-timed memory, low power, SRAM, statistical design
26Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang A GALS Infrastructure for a Massively Parallel Multiprocessor. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
26Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou Circuits for energy harvesting sensor signal processing. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory
26Robert B. Reese, Mitchell A. Thornton, Cherrice Traver A Coarse-Grain Phased Logic CPU. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines
26Mukul Khandelia, Shuvra S. Bhattacharyya Contention-Conscious Transaction Ordering in Embedded Multiprocessors. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF self-timed scheduling, multiprocessor synchronization, interprocessor communication, dataflow programming, embedded multiprocessors
26Ajay Khoche, Erik Brunvand Critical hazard free test generation for asynchronous circuits. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm
26Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee Latency-constrained Resynchronization for Multiprocessor DSP Implementation. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF static multi-processor schedules, iterative dataflow programs, self-timed execution, latency, synchronization overhead
26Sandeep Pagey Fast functional testing of delay-insensitive circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
26Bret Stott, Dave Johnson 0003, Venkatesh Akella Asynchronous 2-D discrete cosine transform core processor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
25Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger Early evaluation for performance enhancement in phased logic. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Harri Lampinen, Olli Vainio Current-sensing completion detection method for standard cell based digital system design. Search on Bibsonomy ISCAS (5) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiprocessor implementation, synchronization, dataflow, static scheduling, iterative computation
24Leonid Ya. Rosenblum, Alexandre Yakovlev Signal Graphs: From Self-Timed to Timed Ones. Search on Bibsonomy PNPM The full citation details ... 1985 DBLP  BibTeX  RDF
22Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Raphael Berner, Patrick Lichtsteiner, Tobi Delbrück Self-timed vertacolor dichromatic vision sensor for low power pattern detection. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Fu-Chiung Cheng, Shu-Ming Chang, Chi-Huam Shieh Detection and Generation of Self-Timed Pipelines from High Level Specifications. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Gennette Gill, John Hansen, Montek Singh Loop pipelining for high-throughput stream computation using self-timed rings. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Scott Fairbanks, Simon W. Moore Self-Timed Circuitry for Global Clocking. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Yousuke Takada, Teijiro Isokawa, Ferdinand Peper, Nobuyuki Matsui Universal Construction on Self-Timed Cellular Automata. Search on Bibsonomy ACRI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22W. Kuang, J. S. Yuan, Abdel Ejnioui Supply Voltage Scalable System Design Using Self-Timed Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Ajanta Chakraborty, Mark R. Greenstreet Efficient Self-Timed Interfaces for Crossing Clock Domains. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Shuji Sannomiya, Yoichi Omori, Makoto Iwata A Macroscopic Behavior Model for Self-Timed Pipeline Systems. Search on Bibsonomy PADS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Christophe Bobda A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22W. Kuang, J. S. Yuan An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver Generalized Early Evaluation in Self-Timed Circuits. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Martin Feldhofer, Thomas Trathnigg, Bernd Schnitzer A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography. Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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