Search results for "set-associative"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	André Seznec, François Bodin	Skewed-associative Caches.	PARLE	1993	DBLP DOI BibTeX RDF	skewed-associative cache, cache, microprocessors, set-associative cache
63	Brannon Batson, T. N. Vijaykumar	Reactive-Associative Caches.	IEEE PACT	2001	DBLP DOI BibTeX RDF
57	Jia-Jhe Li, Yuan-Shin Hwang	Snug set-associative caches: reducing leakage power while improving performance.	ISLPED	2005	DBLP DOI BibTeX RDF	leakage power, set-associative caches
56	Yuguang Wu, Richard R. Muntz	Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	coherence by invalidation, stack evaluation, simulation, Cache memory, set-associative
55	Mohsen Sharifi, Behrouz Zolfaghari	YAARC: yet another approach to further reducing the rate of conflict misses.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Skewed associative cache, YAARC cache, Hit rate, Cache, Conflict misses
55	Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar	A way-halting cache for low-energy high-performance systems.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, dynamic optimization, low energy
49	Peter Sanders 0001	Accessing Multiple Sequences Through Set Associative Caches.	ICALP	1999	DBLP DOI BibTeX RDF	multi merge, memory hierarchy, external memory algorithm, Set associative cache
49	Rabin A. Sugumar, Santosh G. Abraham	Set-Associative Cache Simulation Using Generalized Binomial Trees	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	all-associativity simulation, binomial tree, inclusion properties, single-pass simulation, trace-driven simulation, cache modeling, set-associative caches
48	James C. Browne, Kevin Kane, Hongxia Tian	An Associative Broadcast Based Coordination Model for Distributed Processes.	COORDINATION	2002	DBLP DOI BibTeX RDF
45	Prasanna Palsodkar, Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar	An Approach for Four Way Set Associative Multilevel CMOS Cache Memory.	KES (1)	2007	DBLP DOI BibTeX RDF
42	Masamichi Takagi, Kei Hiraki	Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches.	ICS	2004	DBLP DOI BibTeX RDF	cache memory, replacement algorithm, set-associative cache
41	Rui Min, Wen-Ben Jone, Yiming Hu	Location cache: a low-power L2 cache system.	ISLPED	2004	DBLP DOI BibTeX RDF	L1/L2 caches, data location, power, TLB, set-associative caches
41	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
38	Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi	Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies.	ARES	2009	DBLP DOI BibTeX RDF
37	Michael D. Powell, Amit Agarwal 0001, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy 0001	Reducing set-associative cache energy via way-prediction and selective direct-mapping.	MICRO	2001	DBLP DOI BibTeX RDF
35	Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar	A way-halting cache for low-energy high-performance systems.	ISLPED	2004	DBLP DOI BibTeX RDF	low power techniques, cache design
34	S. Subha	A Set Associative Cache Architecture.	ITNG	2010	DBLP DOI BibTeX RDF	Set Associative mapping, XOR mapping
34	John Stuart Harper, Darren J. Kerbyson, Graham R. Nudd	Analytical Modeling of Set-Associative Cache Behavior.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, data locality, Cache modeling, set-associative, cache interference
34	Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu	Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Stack simulation, V/R-type cache, pseudonym, set-associative cache, synonym, miss ratio
34	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
31	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001	Tolerating process variations in large, set-associative caches: The buddy cache.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	caches, Processor architectures, fault recovery, memory structures
31	Yuan-Shin Hwang, Jia-Jhe Li	Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Caches, leakage power, drowsy caches, cache decay
30	S. Subha	A Set Associative Cache Model with Energy Saving.	ITNG	2008	DBLP DOI BibTeX RDF	Cache, Energy Savings
30	Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone	Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Megalingam Rajesh Kannan, K. B. Deepu, Joseph P. Iype, Ravishankar Parthasarathy, Popuri Gautham	Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor.	BAIP	2010	DBLP DOI BibTeX RDF
30	Seiichiro Fujii, Toshinori Sato	Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.	EUC	2004	DBLP DOI BibTeX RDF
30	Randall T. White, Christopher A. Healy, David B. Whalley, Frank Mueller 0001, Marion G. Harmon	Timing Analysis for Data Caches and Set-Associative Caches.	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF
29	Hamid R. Zarandi, Seyed Ghassem Miremadi	Hierarchical Multiple Associative Mapping in Cache Memories.	ECBS	2005	DBLP DOI BibTeX RDF
29	Jung-Wook Park, Cheong-Ghil Kim, Jung-Hoon Lee, Shin-Dug Kim	An energy efficient cache memory architecture for embedded systems.	SAC	2004	DBLP DOI BibTeX RDF	selective way access, skewed associativity, embedded system, memory hierarchy, low power cache
29	Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim	Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.	ICCD	2004	DBLP DOI BibTeX RDF
28	Sangmin Seo, Jaejin Lee, Zehra Sura	Design and implementation of software-managed caches for multicores with local memory.	HPCA	2009	DBLP DOI BibTeX RDF
28	Rui Min, Yiming Hu	Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Novel memory architectures, cache, memory systems, TLB, performance enhancement
28	Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John	Modeling and Analysis of The Difference-Bit Cache.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	hit access time, cache mapping strategies*, Cache memory, critical path
28	Rabin A. Sugumar, Santosh G. Abraham	Efficient Simulation of Caches under Optimal Replacement with Applications to Miss Characterization.	SIGMETRICS	1993	DBLP DOI BibTeX RDF
27	Yoav Etsion, Dror G. Feitelson	L1 Cache Filtering Through Random Selection of Memory References.	PACT	2007	DBLP DOI BibTeX RDF
27	Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu	Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology.	ASPLOS	1998	DBLP DOI BibTeX RDF
27	Jaume Abella 0001, Antonio González 0001	Heterogeneous way-size cache.	ICS	2006	DBLP DOI BibTeX RDF	adaptive, low power, cache memories, set-associative
27	Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe	Cache modeling for real-time software: beyond direct mapped instruction caches.	RTSS	1996	DBLP DOI BibTeX RDF	direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system
26	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
23	Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras	Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
23	Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras	Applying Decay to Reduce Dynamic Power in Set-Associative Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
23	Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke	Compiler-managed partitioned data caches for low power.	LCTES	2007	DBLP DOI BibTeX RDF	hardware/software co-managed cache, instruction-driven cache management, partitioned cache, low-power, embedded processor
23	Moinuddin K. Qureshi, David Thompson, Yale N. Patt	The V-Way Cache: Demand Based Associativity via Global Replacement.	ISCA	2005	DBLP DOI BibTeX RDF
22	Sebastian Altmeyer, Claire Maiza, Jan Reineke 0001	Resilience analysis: tightening the CRPD bound for set-associative caches.	LCTES	2010	DBLP DOI BibTeX RDF	cache-related preemption delay, lru caches, timing analysis
22	Mrinmoy Ghosh, Emre Özer 0001, Simon Ford, Stuart Biles, Hsien-Hsin S. Lee	Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, bloom filter
22	Clément Ballabriga, Hugues Cassé, Pascal Sainrat	An improved approach for set-associative instruction cache partial analysis.	SAC	2008	DBLP DOI BibTeX RDF	WCET computation, partial cache analysis, partial static analysis, abstract interpretation, COTS, instruction cache
22	SangKyun Yun	Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator.	SAMOS	2006	DBLP DOI BibTeX RDF
22	Jaume Abella 0001, Antonio González 0001	SAMIE-LSQ: set-associative multiple-instruction entry load/store queue.	IPDPS	2006	DBLP DOI BibTeX RDF
22	Stefanos Kaxiras, Georgios Keramidas	IPStash: a set-associative memory approach for efficient IP-lookup.	INFOCOM	2005	DBLP DOI BibTeX RDF
22	Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami	A Low Energy Set-Associative I-Cache with Extended BTB.	ICCD	2002	DBLP DOI BibTeX RDF
22	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
22	Jun Xu 0014, Mukesh Singhal	Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Flow table, performance analysis, router architecture, universal hashing
21	J. Adam Butts, Gurindar S. Sohi	Use-Based Register Caching with Decoupled Indexing.	ISCA	2004	DBLP DOI BibTeX RDF
21	Stefanos Kaxiras, Georgios Keramidas	IPStash: a Power-Efficient Memory Architecture for IP-lookup.	MICRO	2003	DBLP DOI BibTeX RDF	IP
20	André Seznec	Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	multiple page size, skewed associativity, TLB
19	Fong Pong, Nian-Feng Tzeng	HaRP: Rapid Packet Classification via Hashing Round-Down Prefixes.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	filter data sets, incremental rule updates, IP prefixes, set-associative hash tables, tuple space search, decision trees, hashing functions, routers, packet classification, Classification rules
19	Salvador Petit, Julio Sahuquillo, Jose M. Such, David R. Kaeli	Exploiting temporal locality in drowsy cache policies.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	drowsy cache policies, reuse information, low-power, temporal locality, set-associative caches
19	Mark D. Hill, Alan Jay Smith	Evaluating Associativity in CPU Caches.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	CPU caches, cache miss ratio, forest simulation, all-associativity simulation, stack simulation, associativity, buffer storage, content-addressable storage, direct-mapped, set-associative
19	Kimming So, Rudolph N. Rechtschaffen	Cache Operations by MRU Change.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	MRU change, most recently used, prefetch algorithms, performance evaluation, performance, storage management, CPU, content-addressable storage, virtual storage, replacement algorithms, memory access, cache simulation, set associative caches
19	James E. Smith, James R. Goodman	Instruction Cache Replacement Policies and Organizations.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	fully associative, loop model, Cache memories, replacement algorithms, memory organization, direct-mapped, set-associative
17	Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, Charles C. Weems	Using the Compiler to Improve Cache Replacement Decisions.	IEEE PACT	2002	DBLP DOI BibTeX RDF
16	Hongwei Zhou, Chengyi Zhang, Mingxuan Zhang	Improved Way Prediction Policy for Low-Energy Instruction Caches.	ICESS	2007	DBLP DOI BibTeX RDF
16	Jih-Kwon Peir, Windsor W. Hsu, Honesty C. Young, Shauchi Ong	Improving Cache Performance with Balanced Tag and Data Paths.	ASPLOS	1996	DBLP DOI BibTeX RDF
15	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
15	Wei Song 0002, Zihan Xue, Jinchi Han, Zhenzhen Li, Peng Liu 0005	Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
15	Michael A. Bender, Rathish Das, Martin Farach-Colton, Guido Tagliavini	An Associativity Threshold Phenomenon in Set-Associative Caches.	CoRR	2023	DBLP DOI BibTeX RDF
15	Michael A. Bender, Rathish Das, Martin Farach-Colton, Guido Tagliavini	An Associativity Threshold Phenomenon in Set-Associative Caches.	SPAA	2023	DBLP DOI BibTeX RDF
15	Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu	ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.	ICCAD	2022	DBLP DOI BibTeX RDF
15	Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen	Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup.	DATE	2021	DBLP DOI BibTeX RDF
15	Wei Zhang 0173, Nan Guan, Lei Ju 0001, Yue Tang 0001, Weichen Liu, Zhiping Jia	Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
15	Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar	Bounding Cache Persistence Reload Overheads for Set-Associative Caches.	RTCSA	2020	DBLP DOI BibTeX RDF
15	Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti	Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
15	Payman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi	R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays.	ICCD	2018	DBLP DOI BibTeX RDF
15	Wenming Li, Lingjun Fan, Zihou Wang, Xiaochun Ye, Da Wang, Hao Zhang 0009, Liang Zhang, Dongrui Fan, Xianghui Xie 0001	Thread ID based power reduction mechanism for multi-thread shared set-associative caches.	IGSC	2015	DBLP DOI BibTeX RDF
15	Wei Zhang 0044, Hang Zhang 0031, John C. Lach	Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup.	ISLPED	2015	DBLP DOI BibTeX RDF
15	Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors	Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3).	DATE	2014	DBLP DOI BibTeX RDF
15	Pavlos Maniotis, D. Fitsios, George T. Kanellos, Nikos Pleros	A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors.	OFC	2014	DBLP DOI BibTeX RDF
15	Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors	Speculative tag access for reduced energy dissipation in set-associative L1 data caches.	ICCD	2013	DBLP DOI BibTeX RDF
15	Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe	A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems.	J. Inf. Process.	2012	DBLP DOI BibTeX RDF
15	Marjan Gusev, Sasko Ristov	Performance Gains and Drawbacks using Set Associative Cache.	J. Next Gener. Inf. Technol.	2012	DBLP DOI BibTeX RDF
15	C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam	Way Sharing Set Associative Cache Architecture.	VLSI Design	2012	DBLP DOI BibTeX RDF
15	Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Software-Based Self-Test of Set-Associative Cache Memories.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
15	Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem	Advanced hashing schemes for packet forwarding using set associative memory architectures.	J. Parallel Distributed Comput.	2011	DBLP DOI BibTeX RDF
15	Sungjae Lee, Jin-Ku Kang, Inhwan Lee	Way-lookup buffer for low-power set-associative cache.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
15	Yun Liang 0001, Tulika Mitra	Improved procedure placement for set associative caches.	CASES	2010	DBLP DOI BibTeX RDF
15	Benjamin Lesage, Damien Hardy, Isabelle Puaut	WCET Analysis of Multi-Level Set-Associative Data Caches.	WCET	2009	DBLP BibTeX RDF
15	Claire Burguière, Jan Reineke 0001, Sebastian Altmeyer	Cache-Related Preemption Delay Computation for Set-Associative Caches - Pitfalls and Solutions.	WCET	2009	DBLP BibTeX RDF
15	Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem	Progressive hashing for packet processing using set associative memory.	ANCS	2009	DBLP DOI BibTeX RDF
15	Jonathan R. Haigh, Lawrence T. Clark	High performance set associative translation lookaside buffers for low power microprocessors.	Integr.	2008	DBLP DOI BibTeX RDF
15	Damien Hardy, Isabelle Puaut	WCET analysis of multi-level set-associative instruction caches	CoRR	2008	DBLP BibTeX RDF
15	Clément Ballabriga, Hugues Cassé	Improving the First-Miss Computation in Set-Associative Instruction Caches.	ECRTS	2008	DBLP DOI BibTeX RDF
15	Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Applying March Tests to K-Way Set-Associative Cache Memories.	ETS	2008	DBLP DOI BibTeX RDF	cache memories, memory test, march test
15	Damien Hardy, Isabelle Puaut	WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches.	RTSS	2008	DBLP DOI BibTeX RDF
15	Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao	Cycle-time-aware sequential way-access set-associative cache for low energy consumption.	APCCAS	2008	DBLP DOI BibTeX RDF
15	Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan 0001	An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.	ESA	2007	DBLP BibTeX RDF
15	Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau	Using a Way Cache to Improve Performance of Set-Associative Caches.	ISHPC	2005	DBLP DOI BibTeX RDF
15	José Luis Hamkalo, Andrés Djordjalian, Bruno Cernuschi-Frías	A Shared-Way Set Associative On-Chip Cache.	Int. J. Comput. Their Appl.	2004	DBLP BibTeX RDF
15	James D. Fix	The set-associative cache performance of search trees.	SODA	2003	DBLP BibTeX RDF
15	Perng-Fei Lin, James B. Kuo	A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
15	Perng-Fei Lin, James B. Kuo	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF