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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 206 occurrences of 140 keywords
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Results
Found 172 publication records. Showing 172 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
121 | Michael Nicolaidis |
Shorts in self-checking circuits. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
113 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
112 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
79 | Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi |
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
66 | Naveen Amblee, Tung Bui 0001 |
The Impact of Additional Electronic Word-of-Mouth on Sales of Digital Micro-products over Time: A Longitudinal Analysis of Amazon Shorts. |
HICSS |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Rosa Rodríguez-Montañés, Joan Figueras |
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
IDDQ testability, CMOS, deep-submicron |
62 | Vinay Dabholkar, Sreejit Chakravarty |
Computing Stress Tests for Gate Oxide Shorts. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
burn-in, stress tests, gate oxide shorts |
62 | Peter Dahlgren, Peter Lidén |
A fault model for switch-level simulation of gate-to-drain shorts. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
switch-level simulation, gate-to-drain shorts, transistor-level bridging faults, network primitive, electrical-level analysis, algorithm, fault diagnosis, fault model, iteration, integrated circuit modelling, subnetworks |
61 | Walter W. Weber, Adit D. Singh |
An experimental evaluation of the differential BICS for IDDQ testing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices |
52 | Bram Kruseman, Stefan van den Oetelaar |
Detection of Resistive Shorts in Deep Sub-micron Technologies. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
52 | José T. de Sousa, Peter Y. K. Cheung |
Diagnosis of Boards for Realistic Interconnect Shorts. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
interconnect diagnosis, board testing, board diagnosis |
52 | José T. de Sousa, Peter Y. K. Cheung |
Improved diagnosis of realistic interconnect shorts. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Joel W. Gannett |
SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
52 | M. Sytrzycki |
Modeling of gate oxide shorts in MOS transistors. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
49 | Prajit T. Rajendran, Kevin Creusy, Vivien Garnes |
Shorts on the Rise: Assessing the Effects of YouTube Shorts on Long-Form Video Content. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
48 | Hong Hao, Edward J. McCluskey |
Analysis of Gate Oxide Shorts in CMOS Circuits. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
resistance dependence, voltage dependence, pattern dependence, logic gate operation, p-channel transistors, n-channel transistors, CMOS integrated circuits, integrated logic circuits, CMOS circuits, logic gates, defect models, temperature dependence, gate oxide shorts, semiconductor device models |
41 | Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters |
Test quality analysis and improvement for an embedded asynchronous FIFO. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura |
Current Testable Design of Resistor String DACs. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
41 | David C. Keezer, K. E. Newman, John S. Davis |
Improved sensitivity for parallel test of substrate interconnections. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Detecting resistive shorts for CMOS domino circuits. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins |
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
fault modeling, physical defects, gate oxide short |
37 | Jian Liu, Rafic Z. Makki |
Power supply current detectability of SRAM defects. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect |
27 | Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Small-delay defects, pattern grading, pattern selection, ATPG |
27 | José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001 |
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Olivier Rizzo, Hanno Melzner |
Concurrent Wire Spreading, Widening, and Filling. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Bram Kruseman, Stefan van den Oetelaar, Josep Rius 0001 |
Comparison of IDDQ Testing and Very-Low Voltage Testing. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
27 | Thomas W. Williams, Stephen K. Sunter |
How Should Fault Coverage Be Defined? |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Evanthia Papadopoulou, D. T. Lee |
Critical area computation via Voronoi diagrams. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001 |
Analyzing the Need for ATPG Targeting GOS Defects. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi |
Structural diagnosis of interconnects by coloring. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
interconnect, diagnosis, graph coloring, syndrome, balanced code |
27 | Evanthia Papadopoulou, D. T. Lee |
Critical area computation - a new approach. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Yuejian Wu, Sanjay Gupta |
Built-In Self-Test for Multi-Port RAMs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST) |
27 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
27 | T. Ghewala |
CrossCheck: A Cell Based VLSI Testability Solution. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Chihyun Cho, Jae-Yong Kwon, Tae-Weon Kang, Hyunji Koo, Woohyun Chung |
Design of a Waveguide Calibration Kit Consisting of Offset Shorts for Low Measurement Uncertainty. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Caroline Violot, Tugrulcan Elmas, Igor Bilogrevic, Mathias Humbert |
Shorts vs. Regular Videos on YouTube: A Comparative Analysis of User Engagement and Content Creation Trends. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Rahul Kapoor, Nelishia Pillay |
A genetic programming approach to the automated design of CNN models for image classification and video shorts creation. |
Genet. Program. Evolvable Mach. |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Yi Yang, Hao Feng, Yiming Cheng, Zhu Han 0001 |
Emotion-Aware Scene Adaptation: A Bandwidth-Efficient Approach for Generating Animated Shorts. |
Sensors |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Caroline Violot, Tugrulcan Elmas, Igor Bilogrevic, Mathias Humbert |
Shorts vs. Regular Videos on YouTube: A Comparative Analysis of User Engagement and Content Creation Trends. |
WebSci |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Kurtis Ashcroft, Tony Robinson, Joan Condell, Victoria Penpraze, Andrew White, Stephen P. Bird |
An Investigation of Surface EMG Shorts-Derived Training Load during Treadmill Running. |
Sensors |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Yue Cheng, Rodolphe Bailly, Bhushan Borotikar, Claire Scavinner-Dorval, Benjamin Fouquet, Douraied Ben Salem, Sylvain Brochard, François Rousseau 0002 |
Morphological analysis of ankle shorts bones of children with cerebral palsy: a comparative study. |
Medical Imaging: Image Processing |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Wyatt Olson, Freesoul El Shabazz-Thompson, Melanie Wells, Janey Yee, Julia R. Saimo, Bill Xiong, Brock Craft, Audrey Desjardins |
Exposing Tensions in Documentary Filmmaking for Design Research: The Inner Ear Shorts. |
Conference on Designing Interactive Systems (Companion Volume) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Khadijeh Mohammad Naser, Sherin Alamassi, Zuhrieh A. Shanaa, Maryam Abualrish, Emad M. Alghazo, Eman Ali Zaitoun, Enas Said Abulibdeh, Azhar Shater |
Enhancing Postgraduate Learning Achievement: A Microlearning Approach with Reels and Shorts. |
SNAMS |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Natarajan Shanmugam, Srinivasan Gopal, Balasubramanian Madanmohan, S. P. Balaji, Rajesh Rajamani |
Diagnosis of Inter-Turn Shorts of Loaded Transformer Under Various Load Currents and Power Factors; Impulse Voltage-Based Frequency Response Approach. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
25 | David Saucier, Samaneh Davarzani, Reuben F. Burch V., Harish Chander, Lesley Strawderman, Charles E. Freeman, Logan Ogden, Adam Petway, Aaron Duvall, Collin Crane, Anthony Piroli |
External Load and Muscle Activation Monitoring of NCAA Division I Basketball Team Using Smart Compression Shorts. |
Sensors |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. |
VTS |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Dániel Marx |
Four Shorts Stories on Surprising Algorithmic Uses of Treewidth. |
Treewidth, Kernels, and Algorithms |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. |
ITC |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Suman Kalyan Maity, Anshit E. Chaudhary, Animesh Mukherjee 0001 |
"Woman-Metal-White vs Man-Dress-Shorts": Combining Social, Temporal and Image Signals to Understand Popularity of Pinterest Fashion Boards. |
ICWSM |
2019 |
DBLP BibTeX RDF |
|
25 | Suman Kalyan Maity, Anshit E. Chaudhary, Animesh Mukherjee 0001 |
"Woman-Metal-White vs Man-Dress-Shorts": Combining Social, Temporal and Image Signals to Understand Popularity of Pinterest Fashion Boards. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
25 | Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas |
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. |
J. Electron. Test. |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas |
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. |
DATE |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Jeff Chamberlain, Ben Dai, Kevin Vander Jagt, Ben Deda, Hunter Grant, Mike Hardison, David Stephens |
Blizzard Entertainment presents: the making of the "Overwatch Animated Shorts". |
SIGGRAPH Production Sessions |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Sivakumar Nadarajan, Sanjib Kumar Panda, Bicky Bhangu, Amit Kumar Gupta |
Online Model-Based Condition Monitoring for Brushless Wound-Field Synchronous Generator to Detect and Diagnose Stator Windings Turn-to-Turn Shorts Using Extended Kalman Filter. |
IEEE Trans. Ind. Electron. |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas |
Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks. |
MASCOTS |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka |
A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks. |
HPCC/SmartCity/DSS |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee |
Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya |
A topology-agnostic test model for link shorts in on-chip networks. |
SMC |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas |
An on-line test solution for addressing interconnect shorts in on-chip networks. |
IOLTS |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Alyssa Hyduk, Adam Worrall |
"Shorts last sunday, snow pants today": Delving into the information values of immigrant and expatriate users of twitter. |
ASIST |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Libor Pína, Jan Vobecký |
High-power silicon P-i-N diode with cathode shorts: The impact of electron irradiation. |
Microelectron. Reliab. |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Marianne Winslett |
Dennis Shasha speaks out: on how puzzles helped his career, what drives him to write, how we can help biologists, the principles underlying database tuning, why he wears shorts all year, and more. |
SIGMOD Rec. |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Isaac Kerlow |
Storytelling for computer-animated shorts. |
SIGGRAPH ASIA (Courses) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill |
Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. |
IPSJ Trans. Syst. LSI Des. Methodol. |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Marcos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski |
Diagnosis of interconnect shorts in mesh NoCs. |
NOCS |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak |
How to consider shorts and guarantee yield rate improvement for redundant wire insertion. |
ICCAD |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Pablo Maqueda, Josep Rius 0001 |
Analysis of the extra delay on interconnects caused by resistive opens and shorts. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. |
IEICE Trans. Inf. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Viktor Dubec, Sergey Bychikhin, Dionyz Pogany, Erich Gornik, Tilo Brodbeck, Wolfgang Stadler |
Backside interferometric methods for localization of ESD-induced leakage current and metal shorts. |
Microelectron. Reliab. |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Naveen Amblee, Tung X. Bui |
The Impact of Electronic-Word-of-Mouth on Digital Microproducts: An Empirical Investigation of Amazon Shorts. |
ECIS |
2007 |
DBLP BibTeX RDF |
|
25 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu |
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu |
Diagnosis of Transistor Shorts in Logic Test Environment. |
ATS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong |
Testing for Resistive Shorts in FPGA Interconnects. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada |
A test circuit for pin shorts generating oscillation in CMOS logic circuits. |
Syst. Comput. Jpn. |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Zaid Al-Ars, Ad J. van de Goor |
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Erik H. Ingermann, James F. Frenzel |
Behavior of a radiation-immune CMOS logic family under resistive shorts. |
IEEE Trans. Reliab. |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Pranab K. Nag, Wojciech Maly |
Hierarchical extraction of critical area for shorts in very large ICs. |
DFT |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Richard McGowen, F. Joel Ferguson |
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. |
EDAC-ETC-EUROASIC |
1994 |
DBLP DOI BibTeX RDF |
|
25 | C.-J. Chen, Samiha Mourad |
Gate-to-channel shorts in BiCMOS logic gates. |
VTS |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Richard McGowen, F. Joel Ferguson |
Eliminating undetectable shorts between horizontal wires during channel routing. |
VTS |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee |
Testing CMOS Logic Gates for Realistic Shorts. |
ITC |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Warren H. Debany Jr. |
Coverage of Node Shorts Using Internal Access and Equivalence Classes. |
VLSI Design |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Warren H. Debany Jr. |
Measuring the coverage of node shorts by internal access methods. |
VTS |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Hong Hao, Edward J. McCluskey |
"Resistive Shorts" Within CMOS Gates. |
ITC |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Jerry M. Soden, Charles F. Hawkins |
Test Considerations for Gate Oxide Shorts in CMOS ICs. |
IEEE Des. Test |
1986 |
DBLP DOI BibTeX RDF |
|
25 | Jerry M. Soden, Charles F. Hawkins |
Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs. |
ITC |
1986 |
DBLP BibTeX RDF |
|
25 | Jerry M. Soden, Charles F. Hawkins |
Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs. |
ITC |
1985 |
DBLP BibTeX RDF |
|
25 | John M. Acken |
Testing for bridging faults (shorts) in CMOS circuits. |
DAC |
1983 |
DBLP BibTeX RDF |
|
24 | Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle |
Transient power supply current monitoring - A new test method for CMOS VLSI circuits. |
J. Electron. Test. |
1995 |
DBLP DOI BibTeX RDF |
Design for current-testability, drain/source opens, floating gates, shorts, transient power supply current |
24 | Steven D. McEuen |
Reliability benefits of IDDQ. |
J. Electron. Test. |
1992 |
DBLP DOI BibTeX RDF |
reliability, I DDQ, Gate oxide shorts |
24 | Jaume A. Segura 0001, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio |
Quiescent current analysis and experimentation of defective CMOS circuits. |
J. Electron. Test. |
1992 |
DBLP DOI BibTeX RDF |
Bridging failures, floating gate opens, intentionally designed defective circuits defects, current testing, defect modeling, gate oxide shorts |
14 | Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty |
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing |
14 | Allen Sayegh, Peter Mabardi, David Register, Daniel Spann, Jonathan Lu, Amanda Parkes, S. Adrian Massey III |
Home, work, (play). |
CHI Extended Abstracts |
2009 |
DBLP DOI BibTeX RDF |
hyper-reality, integration, gesture, spatial, augmented |
14 | Pallav Gupta, Rui Zhang, Niraj K. Jha |
Automatic Test Generation for Combinational Threshold Logic Networks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Khadidja Saidi, Youcef Remram, Mokhtar Attari |
Conception of an ultrasonic system for assistance to the diagnosis of the osteoporosis. |
EIT |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Jie Zhang 0007, Nishant Patil, Subhasish Mitra |
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
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