Search results for "sign-magnitude"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
32	Mi Lu, Jen-Shiun Chiang	A Novel Division Algorithm for the Residue Number System.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	sign magnitude arithmetic division, signed number division, overflow detection, digital arithmetic, search problems, residue number system, number theory, binary search, algorithm theory, dividing circuits, parity checking, sign detection, division algorithm
32	Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung	Hard-Wired Multipliers with Encoded Partial Products.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement
23	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Hyochan An, Yu Chen 0070, Zichen Fan, Qirui Zhang 0001, Pierre Abillama, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.	ISSCC	2023	DBLP DOI BibTeX RDF
22	Gennaro Di Meo, Davide De Caro, Nicola Petra, Antonio G. M. Strollo	A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section.	PRIME	2022	DBLP DOI BibTeX RDF
22	Oguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating.	DSD	2022	DBLP DOI BibTeX RDF
22	Gayas Mohiuddin Sayed, Matthias Kuhl	Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy.	SBCCI	2022	DBLP DOI BibTeX RDF
22	Oguz Meteer, Marco Jan Gerrit Bekooij	Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing.	DASIP	2021	DBLP DOI BibTeX RDF
22	Francisco José Orts Gómez, Gloria Ortega López, Ester M. Garzón	An optimized quantum circuit for converting from sign-magnitude to two's complement.	Quantum Inf. Process.	2019	DBLP DOI BibTeX RDF
22	Luc Waeijen, Hailong Jiao, Henk Corporaal, Yifan He	Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude.	DSD	2018	DBLP DOI BibTeX RDF
22	Lukas Balles, Philipp Hennig	Dissecting Adam: The Sign, Magnitude and Variance of Stochastic Gradients.	ICML	2018	DBLP BibTeX RDF
22	Aidyn Zhakatayev, Sugil Lee, Hyeon Uk Sim, Jongeun Lee	Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks.	DAC	2018	DBLP DOI BibTeX RDF
22	Saeid Gorgin 0001, Ghassem Jaberipur	Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
22	Slava Voloshynovskiy, Taras Holotyak, Fokko Beekhof	Soft Content Fingerprinting With Bit Polarization Based on Sign-Magnitude Decomposition.	IEEE Trans. Inf. Forensics Secur.	2015	DBLP DOI BibTeX RDF
22	Svyatoslav Voloshynovskiy, Taras Holotyak, Oleksiy J. Koval, Fokko Beekhof, Farzad Farhadzadeh	Sign-magnitude decomposition of mutual information with polarization effect in digital identification.	ITW	2011	DBLP DOI BibTeX RDF
21	Charles G. Boncelet Jr.	Lossless Image Compression with BCTW.	ICIP	2006	DBLP DOI BibTeX RDF
21	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Analytical estimation of signal transition activity from word-level statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
10	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Stuart F. Oberman, Michael Y. Siu	A High-Performance Area-Efficient Multifunction Interpolator.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
10	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
10	Nikolaus Voß, Bärbel Mertsching	A Framework for Low Power Audio Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Ahmet T. Erdogan, Tughrul Arslan	Low power block based FIR filtering cores.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang	A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
10	Peter-Michael Seidel, Guy Even	On the Design of Fast IEEE Floating-Point Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
10	V. A. Bartlett, Eckhard Grass	A Low-Power Asynchronous VLSI FIR Filter.	ARVLSI	2001	DBLP DOI BibTeX RDF
10	Parag K. Lala, Alvernon Walker	On-Line Error Detectable Carry-Free Adder Design.	DFT	2001	DBLP DOI BibTeX RDF	carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
10	Won Namgoong, Teresa H. Meng	Power consumption of parallel spread spectrum correlator architectures.	ISLPED	1998	DBLP DOI BibTeX RDF
10	K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.	Parallel reduced area multipliers.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF