Search results for "silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor	Bridging pre-silicon verification and post-silicon validation.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon, pre-silicon, verification, validation
59	Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici	Post-silicon validation opportunities, challenges and recent advances.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon validation
57	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
57	Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang	Visibility enhancement for silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	silicon validation, functional verification, silicon debug
56	Jagannath Keshava, Nagib Hakim, Chinna Prudvi	Post-silicon validation challenges: how EDA and academia can help.	DAC	2010	DBLP DOI BibTeX RDF	design, verification, test, validation, emulation
54	Lin Xie, Azadeh Davoodi, Kewal K. Saluja	Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon diagnosis, process variations
54	Yu Huang 0005, Wu-Tung Cheng	Using embedded infrastructure IP for SOC post-silicon verification.	DAC	2003	DBLP DOI BibTeX RDF	FPGA core, infrastructure IP (I-IP), post-silicon verification, transaction-based verification
53	Sandip Ray, Warren A. Hunt Jr.	Connecting pre-silicon and post-silicon verification.	FMCAD	2009	DBLP DOI BibTeX RDF
53	A. Richard Newton	Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel).	DAC	1998	DBLP DOI BibTeX RDF
50	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
50	Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak	On Silicon-Based Speed Path Identification.	VTS	2005	DBLP DOI BibTeX RDF
50	Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng	A path-based methodology for post-silicon timing validation.	ICCAD	2004	DBLP DOI BibTeX RDF
48	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	Diagnosing Silicon Failures Based on Functional Test Patterns.	MTV	2006	DBLP DOI BibTeX RDF	fault diagnosis, Silicon debug, design for debug
48	Chirag S. Patel	Silicon carrier for computer systems.	DAC	2006	DBLP DOI BibTeX RDF	chip-package co-design, electrical modeling, micro-bumps, silicon carrier, computer system, CMOS scaling, system on package
45	Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst	Silicon VLSI processing architectures incorporating integrated optoelectronic devices.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
44	Miron Abramovici	In-System Silicon Validation and Debug.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
44	Ilya Wagner, Valeria Bertacco	Reversi: Post-silicon validation system for modern microprocessors.	ICCD	2008	DBLP DOI BibTeX RDF
44	Seiji Kameda, Tetsuya Yagi	An analog silicon retina with multichip configuration.	IEEE Trans. Neural Networks	2006	DBLP DOI BibTeX RDF
42	Christophe Lécuyer, David C. Brock	Biographies.	IEEE Ann. Hist. Comput.	2006	DBLP DOI BibTeX RDF	Gordon Moore, semiconductor industry, silicon technology, silicon device manufacture, Fairchild Semiconductor, Shockley Semiconductor, microprocessor, integrated circuit, DRAM, personal computer, chemistry, Moore's law, Intel
42	Georgios Karakonstantis, Kaushik Roy 0001	Low-Power and Variation-Tolerant Application-Specific System Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Sachin S. Sapatnekar	Statistical Design of Integrated Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee	Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Swaroop Ghosh	Effect of Variations and Variation Tolerance in Logic Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon	Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Wei Zhang 0012, James Williamson, Li Shang	Power Dissipation.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Aditya Bansal, Rahul M. Rao	Variations: Sources and Characterization.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Nikil Mehta, André DeHon	Low-Power Techniques for FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Bipul C. Paul, Arijit Raychowdhury	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Nikil Mehta, André DeHon	Variation and Aging Tolerance in FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Hamid Mahmoodi	Low-Power and Variation-Tolerant Memory Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Meeta Sharma Gupta, Pradip Bose	Variation-Tolerant Microprocessor Architecture at Low Power.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
42	Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim	Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.	SLIP	2009	DBLP DOI BibTeX RDF	wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via
42	Dennis Sylvester, David T. Blaauw, Eric Karl	ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	unpredictable silicon, runtime self-diagnosis, adaptivity, architecture, process variations, self-healing, ElastIC, technology scaling
40	John P. Denton, Sang Woo Pae, Gerold W. Neudeck	Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	SOI MOSFET, selective epitaxial growth, silicon, silicon on insulator, thin film SOI, three dimensional circuits
38	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
38	Eli Yablonovitch	Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?	ICCAD	2007	DBLP DOI BibTeX RDF
38	Ernst Rank, Ulrich Weinert	A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
37	Hee-Dong Kim, Ho-Myoung An, Yujeong Seo, Yongjie Zhang, Jongsun Park 0001, Tae Geun Kim	Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
36	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
36	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	A General Failure Candidate Ranking Framework for Silicon Debug.	VTS	2008	DBLP DOI BibTeX RDF	Silicon Debug
36	Shi-Hua Luo, Jiu-sun Zeng	BF Hot Metal Silicon Content Prediction Using Unsupervised Fuzzy Clustering.	ICFIE	2007	DBLP DOI BibTeX RDF	Silicon Content Prediction, Unsupervised Fuzzy Clustering
36	Xuesong Han	Investigation of Surface Integrity in the Case of Chemical Mechanical Polishing Silicon Wafer by Molecular Dynamics Simulation Method.	ICAT	2006	DBLP DOI BibTeX RDF	silicon wafer, vacancy, dislocation, molecular dynamics, Chemical mechanical polishing
36	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel	Automatic generation of breakpoint hardware for silicon debug.	DAC	2004	DBLP DOI BibTeX RDF	hardware-breakpoints, design-flow, silicon-debug, design-for-debug
36	R. Dean Adams, Phil Shephard III	Silicon-on-Insulator Technology Impacts on SRAM Testing.	VTS	2000	DBLP DOI BibTeX RDF	Fault modeling and simulation, Silicon On Insulator (SOI), Memory testing
36	Robert C. Frye, King L. Tai, Maureen Y. Lau, Thaddeus J. Gabara	Trends in Silicon-On-Silicon Multichip Modules.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
35	Soon Fatt Yoon	III-V/Si integration: potential and outlook for integrated low power micro and nanosystems.	CASES	2009	DBLP DOI BibTeX RDF	heterogeneous integration
33	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
33	Jing Li 0073, Aditya Bansal, Swaroop Ghosh, Kaushik Roy 0001	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
33	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
33	Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir	Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.	DAC	2010	DBLP DOI BibTeX RDF	data mining, learning, timing analysis, delay test
33	Mahesh Ketkar, Eli Chiprout	A microarchitecture-based framework for pre- and post-silicon power delivery analysis.	MICRO	2009	DBLP DOI BibTeX RDF
33	Jürgen Kogler, Christoph Sulzbachner, Wilfried Kubinger	Bio-inspired Stereo Vision System with Silicon Retina Imagers.	ICVS	2009	DBLP DOI BibTeX RDF
33	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
33	Kwang-Ting (Tim) Cheng	Effective silicon debug is key for time to money.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
33	Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
33	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Post-silicon verification for cache coherence.	ICCD	2008	DBLP DOI BibTeX RDF
33	Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi	Computing and design for software and silicon manufacturing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
33	R. Takami, Kazuhiro Shimonomura, Seiji Kameda, Tetsuya Yagi	An image pre-processing system employing neuromorphic 100×100 pixel silicon retina [robot vision applications].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
33	Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger	Silicon Symptoms to Solutions: Applying Design for Debug Techniques.	ITC	2002	DBLP DOI BibTeX RDF
33	Ranjit Singh, Low Lee Ngo, Ho Soon Seng, Frederick Neo Chwee Mok	A Silicon Piezoresistive Pressure Sensor.	DELTA	2002	DBLP DOI BibTeX RDF
33	Chung-Yu Wu, Hsin-Chin Jiang	An improved BJT-based silicon retina with tunable image smoothing capability.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
33	Walter Bohmayr, Alexander Burenkov, Jürgen Lorenz, Heiner Ryssel, Siegfried Selberherr	Monte Carlo simulation of silicon amorphization during ion implantation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
33	Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi	DCT/IDCT processor for HDTV developed with dsp silicon compiler.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
33	Abhay B. Bulsari, Henrik Saxén	Artificial Neural Networks for Predicting Silicon Content in Raw Iron From Blast Furnaces.	ICCI	1991	DBLP DOI BibTeX RDF
30	Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
30	Lin Xie, Azadeh Davoodi	Representative path selection for post-silicon timing prediction under variability.	DAC	2010	DBLP DOI BibTeX RDF	process variations, post-silicon validation
30	Qunzeng Liu, Sachin S. Sapatnekar	Synthesizing a representative critical path for post-silicon delay prediction.	ISPD	2009	DBLP DOI BibTeX RDF	post-silicon optimization, representative critical path
30	Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic	Designing multi-socket systems using silicon photonics.	ICS	2009	DBLP DOI BibTeX RDF	multi-socket, silicon photonics
30	Kelageri Nagaraj, Sandip Kundu	Process variation mitigation via post silicon clock tuning.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	post-silicon tuning, performance, process variation
30	Xiao Liu 0011, Qiang Xu 0001	Interconnection fabric design for tracing signals in post-silicon validation.	DAC	2009	DBLP DOI BibTeX RDF	trace-based debug, post-silicon validation
30	XingLong Guo, Yan Jin, Lei Liu, WeiXia Ouyang, ZongSheng Lai	Design and fabrication of miniature antenna based on silicon substrate for wireless communications.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	miniature antenna, high-resistivity silicon (HR-Si), IC process
30	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
30	Joon-Sung Yang, Nur A. Touba	Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.	VTS	2008	DBLP DOI BibTeX RDF	Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR
30	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
30	David Geer	Silicon Optics Aims to Combine the Best of Both Worlds.	Computer	2006	DBLP DOI BibTeX RDF	silicon optics, optical systems, computing technology
30	John R. Long	Next-Generation Narrowband RF Front-Ends in Silicon IC Technology.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	narrowband circuits, silicon IC technology, RF design
30	Bryan Preas, Massoud Pedram, Don Curry	Automatic Layout of Silicon-on-Silicon Hybrid Packages.	DAC	1989	DBLP DOI BibTeX RDF
29	Rosemary M. Francis, Simon W. Moore	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.	FPGA	2009	DBLP DOI BibTeX RDF	tdm wiring, fpga, routing
29	Wei Huang 0004, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan	Differentiating the roles of IR measurement and simulation for power and temperature-aware design.	ISPASS	2009	DBLP DOI BibTeX RDF
29	Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout	Speedpath prediction based on learning from a small set of examples.	DAC	2008	DBLP DOI BibTeX RDF	speedpath, learning, timing analysis
29	Qing K. Zhu, Paige Kolze	Metal Fix and Power Network Repair for SOC.	ISVLSI	2006	DBLP DOI BibTeX RDF
29	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
29	Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron	LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction.	ISQED	2003	DBLP DOI BibTeX RDF
29	Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Satish Iyengar, Alain Pirson	Design of a 17-million gate network processor using a design factory.	DAC	2003	DBLP DOI BibTeX RDF
29	Robert P. Colwell, Bob Brennan	Intel's Formal Verification Experience on the Willamette Development.	TPHOLs	2000	DBLP DOI BibTeX RDF
27	Roel Baets, Ananth Z. Subramanian, Stephane Clemmen, Bart Kuyken, Peter Bienstman, Nicolas Le Thomas, Gunther Roelkens, Dries Van Thourhout, Philippe Hélin, Simone Severi	Silicon photonics: Silicon nitride versus silicon-on-insulator.	OFC	2016	DBLP BibTeX RDF
27	Ricky W. Chuang, Mao-Teng Hsu, Shen-Horng Chou, Yao-Jen Lee	Silicon Mach-Zehnder Waveguide Interferometer on Silicon-on-Silicon (SOS) Substrate Incorporating the Integrated Three-Terminal Field-Effect Device as an Optical Signal Modulation Structure.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
27	John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, John M. Cotte	3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
27	C. K. Wong, Hei Wong, Mansun Chan, Chi-Wah Kok, H. P. Chan	Minimizing hydrogen content in silicon oxynitride by thermal oxidation of silicon-rich silicon nitride.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
27	Ingvar Åberg	Transport in thin-body Metal oxide semiconductor field-effect transistors fabricated in strained silicon and strained silicon/silicon-germanium heterostructures on insulator.		2006	RDF
27	John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, Christian D. Schuster, Christian W. Baks, Fuad E. Doany, Joanna Rosner, Steven Cordes	Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.	CICC	2005	DBLP DOI BibTeX RDF
27	M. C. Poon, Y. Gao, Ted Chi-Wah Kok, A. M. Myasnikov, Hei Wong	SIMS study of silicon oxynitride prepared by oxidation of silicon-rich silicon nitride layer.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
27	Xiang Zhang, Ahmed Louri	A multilayer nanophotonic interconnection network for on-chip many-core communications.	DAC	2010	DBLP DOI BibTeX RDF	interconnection networks, CMP, 3D, silicon photonics
27	Yoonjung Yang, Gilsoo Cho	Novel Stretchable Textile-Based Transmission Bands: Electrical Performance and Appearance after Abrasion/Laundering, and Wearability.	HCI (3)	2009	DBLP DOI BibTeX RDF	stretchable textile-based transmission band, silicon-coated stainless steel multifilament yarn, abrasion, laundering, electrical resistance, MP3 player jacket, wear sensation, image analysis
27	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, heterogeneous, 3d ic, switch box, through silicon via
27	Weiwu Hu, Jian Wang	Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	correlation design, balanced design, Pico-architecture design, work-on-silicon, optimized design, superscalar architecture
27	Shiyan Hu, Jiang Hu	Unified adaptivity optimization of clock and logic signals.	ICCAD	2007	DBLP DOI BibTeX RDF	clock signal tuning, logic signal tuning, post-silicon tuning, robustness, variation
27	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
27	Jari Järvinen, Juha Haataja, Jari Hämäläinen	Industrial Applications: Challenges in Modeling and Computing.	PARA	2000	DBLP DOI BibTeX RDF	multi-physics, paper machines, silicon crystals, Modeling, parallel computing, computing, industry, numerical methods, multi-scale
27	David Parry 0001	Scalability in computing for today and tomorrow.	ARVLSI	1997	DBLP DOI BibTeX RDF	synergistic combination, performance growth, current multiprocessor alternatives, scalable SMP, Silicon Graphics Origin multiprocessor, S/sup 2/MP memory architecture, core technologies, scalability, system architecture, shared-memory multiprocessors, shared memory systems