Search results for "sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
86	Puneet Gupta 0001, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma	Eyecharts: constructive benchmarking of gate sizing heuristics.	DAC	2010	DBLP DOI BibTeX RDF	dynamic programming, benchmarking, gate sizing
80	Chung-Ping Chen, D. F. Wong 0001	Optimal Wire-Sizing Function with Fringing Capacitance Consideration.	DAC	1997	DBLP DOI BibTeX RDF
78	Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal	Optimal wire and transistor sizing for circuits with non-tree topology.	ICCAD	1997	DBLP DOI BibTeX RDF	optimal circuit sizing, crosstalk, Elmore delay, clock distribution networks
75	Jason Cong, Lei He 0001	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
72	Chris C. N. Chu, D. F. Wong 0001	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
70	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
70	Narender Hanchate, Nagarajan Ranganathan	Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
69	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
69	Alain Abran, Marcela Maya	A sizing measure for adaptive maintenance work products.	ICSM	1995	DBLP DOI BibTeX RDF	software sizing measure, adaptive maintenance work products, productivity analysis, sizing technique, software maintenance, software maintenance, software metrics, organization, granularity, software development management, software cost estimation, human resource management, Function Points, productivity models
66	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
64	Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich	Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints.	DATE	1999	DBLP DOI BibTeX RDF
64	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
63	Narender Hanchate, Nagarajan Ranganathan	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
63	William Roshan Quadros, Ved Vyas, Michael L. Brewer, Steven J. Owen, Kenji Shimada	A Computational Framework for Generating Sizing Function in Assembly Meshing.	IMR	2005	DBLP DOI BibTeX RDF	Assembly meshing, finite element mesh sizing function, pre-mesh, skeleton
61	Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
61	Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal	Optimizing dominant time constant in RC circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
60	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
60	Chris C. N. Chu, D. F. Wong 0001	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
57	Vishal Khandelwal, Ankur Srivastava 0001	Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
57	Murari Mani, Mahesh Sharma, Michael Orshansky	Application of fast SOCP based statistical sizing in the microprocessor design flow.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
57	Chris C. N. Chu, D. F. Wong 0001	Greedy wire-sizing is linear time.	ISPD	1998	DBLP DOI BibTeX RDF
57	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
55	Jiang Wu, Zhizhong Li 0003, Jianwei Niu 0003	A 3D Method for Fit Assessment of a Sizing System.	HCI (11)	2009	DBLP DOI BibTeX RDF	fit assessment, sizing system, 3D modeling
55	Paul G. A. Jespers	Sizing CMOS circuits by means of the gm/ID methodology and a compact model.	SBCCI	2008	DBLP DOI BibTeX RDF	circuit sizing
55	Mehdi Hakimi, Seyyed Masoud Moghaddas Tafreshi, M. R. Rajati	Unit Sizing of a Stand-Alone Hybrid Power System Using Model-Free Optimization.	GrC	2007	DBLP DOI BibTeX RDF	reformer, hybrid power system, optimal sizing, particle swarm optimization I. NOMENCLATURE P conv wg - Power delivered from wind turbines to converter (kw) P el wg - Power delivered from wind turbines to electrolyzer (kw) P k el tan - Power delive, K. N. Toosi University of Technology, Tehran-Iran (e-mail: sm_hakimi@yahoo.com). S.M.M.Tafreshi is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: tafreshi@eetd.kntu.ac.ir). M. R. Rajati is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: mohammadreza.rajati@gmail.com). P wt Power generated by wind turbines (kw) Pload Load power (kw) E k tan Stored energy in the hydrogen tank (kwh) fc, el, conv Efficiency of fuel cell, electrolyzer, converter NPCindex Net present cost (the index shows the corresponding component) ($) S Single-payment present worth factor R Life time of project (year) L Life time of each components (year) Ir Inter, fuel cell, wind turbine
55	Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu	Optimal gate sizing for coupling-noise reduction.	ISPD	2004	DBLP DOI BibTeX RDF	coupling-noise, gate-sizing, lattice theory, fixpoint
55	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-route gate sizing for crosstalk noise reduction.	DAC	2003	DBLP DOI BibTeX RDF	crosstalk noise repair, gate sizing
55	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
55	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	ICCAD	1995	DBLP DOI BibTeX RDF	acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications
55	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	An iterative gate sizing approach with accurate delay evaluation.	ICCAD	1995	DBLP DOI BibTeX RDF	delay evaluation, linear program, iteration, gate sizing
53	Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay	Interconnect synthesis without wire tapering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
52	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
52	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
52	Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
49	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
49	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	Sizing Rules for Bipolar Analog Circuit Design.	DATE	2008	DBLP DOI BibTeX RDF
49	Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi	Wire Sizing for Non-Tree Topology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
49	Lakulish Antani, Christophe Delage, Pierre Alliez	Mesh Sizing with Additively Weighted Voronoi Diagrams.	IMR	2007	DBLP DOI BibTeX RDF
49	Jia Wang 0003, Debasish Das, Hai Zhou 0001	Gate sizing by Lagrangian relaxation revisited.	ICCAD	2007	DBLP DOI BibTeX RDF
49	Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang	Switching-activity driven gate sizing and Vth assignment for low power design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
49	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
49	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
49	Yue Chen, Barry W. Boehm, Raymond J. Madachy, Ricardo Valerdi	An Empirical Study of eServices Product UML Sizing Metrics.	ISESE	2004	DBLP DOI BibTeX RDF
49	Ashok K. Murugavel, N. Ranganathan	Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.	VLSI Design	2004	DBLP DOI BibTeX RDF
49	Marko Loparic, Hugues Marchand, Laurence A. Wolsey	Dynamic knapsack sets and capacitated lot-sizing.	Math. Program.	2003	DBLP DOI BibTeX RDF
49	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.	ISPD	2002	DBLP DOI BibTeX RDF
49	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
49	Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral signal path, incremental modeling, small-signal, sequential design space pruning, minimax optimization
49	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
49	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	ICCAD	1994	DBLP DOI BibTeX RDF
49	Edward G. Rodgers	Software sizing problems in software engineering metrics.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF
48	Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
48	Claudio Fabiano Motta Toledo, Paulo Morelato França, Kalianne Almeida Rosa	Evaluating genetic algorithms with different population structures on a lot sizing and scheduling problem.	SAC	2008	DBLP DOI BibTeX RDF	multi-population, soft drink company, genetic algorithms, scheduling, lot sizing
48	Koustav Bhattacharya, Nagarajan Ranganathan	A linear programming formulation for security-aware gate sizing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing
48	Yongjian Li, Jian Chen, Xiaoqiang Cai	An integrated staff-sizing approach considering feasibility of scheduling decision.	Ann. Oper. Res.	2007	DBLP DOI BibTeX RDF	Staff-sizing, Staff flexibility, Multiple objective linear programming (MOLP), Scheduling, Planning
48	Fabrizio Marinelli 0001, Maria Elena Nenni, Antonio Sforza	Capacitated lot sizing and scheduling with parallel machines and shared buffers: A case study in a packaging company.	Ann. Oper. Res.	2007	DBLP DOI BibTeX RDF	Scheduling, Packaging, Lot sizing
48	Yongpei Guan, Shabbir Ahmed 0001, George L. Nemhauser, Andrew J. Miller	A branch-and-cut algorithm for the stochastic uncapacitated lot-sizing problem.	Math. Program.	2006	DBLP DOI BibTeX RDF	Stochastic Lot-Sizing, Multi-stage Stochastic Integer Programming, Polyhedral Study, Branch-and-Cut
48	Fernando G. Lobo, Cláudio F. Lima	A review of adaptive population sizing schemes in genetic algorithms.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	genetic algorithms, population sizing, parameter setting
48	Hiran Tennakoon, Carl Sechen	Efficient and accurate gate sizing with piecewise convex delay models.	DAC	2005	DBLP DOI BibTeX RDF	piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling
48	Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar	Robust gate sizing by geometric programming.	DAC	2005	DBLP DOI BibTeX RDF	posynomial, uncertainty ellipsoid, optimization, gate sizing, geometric program
48	William Roshan Quadros, Kenji Shimada, Steven J. Owen	Skeleton-based computational method for the generation of a 3D finite element mesh sizing function.	Eng. Comput.	2004	DBLP DOI BibTeX RDF	Finite element mesh sizing function, Skeleton, Octree, Medial axis transform
48	Ted J. Wasserman, Patrick Martin 0001, David B. Skillicorn, Haider Rizvi	Developing a characterization of business intelligence workloads for sizing new database systems.	DOLAP	2004	DBLP DOI BibTeX RDF	clustering, workload characterization, business intelligence, sizing, capacity planning
48	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.	ISLPED	2003	DBLP DOI BibTeX RDF	dual threshold, sizing, dual supply voltage, simultaneous
48	Chang Woo Kang, Soroush Abbaspour, Massoud Pedram	Buffer sizing for minimum energy-delay product by using an approximating polynomial.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	short circuit energy, buffer sizing, polynomial approximation
48	M. Y. Y. Leung, John C. S. Lui, Leana Golubchik	Use of Analytical Performance Models for System Sizing and Resource Allocation in Interactive Video-on-Demand Systems Employing Data Sharing Techniques.	IEEE Trans. Knowl. Data Eng.	2002	DBLP DOI BibTeX RDF	data sharing techniques, resource allocation, Video-on-demand, system sizing
48	Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija	CMOS Combinational Circuit Sizing by Stage-wise Tapering.	DATE	1998	DBLP DOI BibTeX RDF	tapering, Transistor sizing, resynthesis
45	I-Min Liu, Adnan Aziz	Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.	ICCD	2000	DBLP DOI BibTeX RDF
45	Chris C. N. Chu, Martin D. F. Wong	A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
41	Xiaochun Zhu, Bo Zhou 0010, Lu Chen	Software testing sizing in incremental development: A case study.	ESEM	2009	DBLP DOI BibTeX RDF
41	Joel Sommers, Paul Barford, Albert G. Greenberg, Walter Willinger	An SLA perspective on the router buffer sizing problem.	SIGMETRICS Perform. Evaluation Rev.	2008	DBLP DOI BibTeX RDF
41	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
41	Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng	An optimal algorithm for sizing sequential circuits for industrial library based designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
41	Xiaoqing Cheng	Performance, Benchmarking and Sizing in Developing Highly Scalable Enterprise Software.	SIPEW	2008	DBLP DOI BibTeX RDF
41	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
41	Mei Wang, Yashar Ganjali	The Effects of Fairness in Buffer Sizing.	Networking	2007	DBLP DOI BibTeX RDF
41	DiaaEldin Khalil, Yehea I. Ismail	Optimum sizing of power grids for IR drop.	ISCAS	2006	DBLP DOI BibTeX RDF
41	Fujita Tomohiro, Iiduka Osamu	Analog circuit sizing with dynamic search window.	ISCAS	2006	DBLP DOI BibTeX RDF
41	Preetam Patil, Varsha Apte	Sizing of IEEE 802.11 wireless LANs.	WMASH	2005	DBLP DOI BibTeX RDF	simulations, wireless LANs, MAC, analytical models
41	Amogh Dhamdhere, Hao Jiang, Constantinos Dovrolis	Buffer sizing for congested Internet links.	INFOCOM	2005	DBLP DOI BibTeX RDF
41	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Postroute gate sizing for crosstalk noise reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
41	Debjit Sinha, Hai Zhou 0001	Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.	ICCAD	2004	DBLP DOI BibTeX RDF
41	Te-Kai Liu, Hui Shen, Santhosh Kumaran	A Capacity Sizing Tool for a Business Process Integration Middleware.	CEC	2004	DBLP DOI BibTeX RDF
41	Ted J. Wasserman, Patrick Martin 0001, Haider Rizvi	Sizing DB2 UDB® servers for business intelligence workloads.	CASCON	2004	DBLP BibTeX RDF	DB2
41	Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis 0001, José Luís Almada Güntzel	A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.	SBCCI	2003	DBLP DOI BibTeX RDF
41	Ruibing Lu, Cheng-Kok Koh	Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.	ICCAD	2003	DBLP DOI BibTeX RDF
41	N. Ranganathan, Ashok K. Murugavel	A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.	ICCD	2003	DBLP DOI BibTeX RDF
41	Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-Route Gate Sizing for Crosstalk Noise Reduction.	ISQED	2003	DBLP DOI BibTeX RDF
41	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
41	James T. Kao, Anantha P. Chandrakasan, Dimitri A. Antoniadis	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.	DAC	1997	DBLP DOI BibTeX RDF
40	Claudio Fabiano Motta Toledo, Lucas de Oliveira, Renato Resende Ribeiro de Oliveira, Marluce Rodrigues Pereira	Parallel genetic algorithm approaches applied to solve a synchronized and integrated lot sizing and scheduling problem.	SAC	2010	DBLP DOI BibTeX RDF	multi-population, soft drink company, scheduling, parallel genetic algorithms, lot sizing
40	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
40	Shoshana Anily, Michal Tzur, Laurence A. Wolsey	Multi-item lot-sizing with joint set-up costs.	Math. Program.	2009	DBLP DOI BibTeX RDF	Multi-item lot-sizing, Joint set-up cost, Extended formulation, Convex hull, Mixed integer programming
40	Yifang Liu, Jiang Hu	A new algorithm for simultaneous gate sizing and threshold voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	threshold voltage assignment, gate sizing
40	Ruichun Yang, Zhen Wang, Dachuan Xu	A Cost-Sharing Method for the Soft-Capacitated Economic Lot-Sizing Game.	COCOA	2009	DBLP DOI BibTeX RDF	Economic lot-sizing game, cost-sharing method, cross- monotonic, approximate cost recovery
40	Jason Cong, John Lee 0002, Lieven Vandenberghe	Robust gate sizing via mean excess delay minimization.	ISPD	2008	DBLP DOI BibTeX RDF	robust gate sizing, process variation, geometric programming, conditional value-at-risk
40	Eleftherios I. Amoiralis, Pavlos S. Georgilakis, Marina A. Tsili, Antonios G. Kladas	Ant Colony System-Based Algorithm for Optimal Multi-stage Planning of Distribution Transformer Sizing.	KES (2)	2008	DBLP DOI BibTeX RDF	Optimal Transformer Sizing, Thermal Loading, Energy Loss Cost, Distribution Network Planning, Transformers, Ant Colony Optimization
40	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
40	Zhanyuan Jiang, Weiping Shi	Circuit-wise buffer insertion and gate sizing algorithm with scalability.	DAC	2008	DBLP DOI BibTeX RDF	buffer insertion, gate sizing, interconnect synthesis
40	Tian-Li Yu 0001, Kumara Sastry, David E. Goldberg, Martin Pelikan	Population sizing for entropy-based model building in discrete estimation of distribution algorithms.	GECCO	2007	DBLP DOI BibTeX RDF	genetic algorithms, entropy, mutual information, estimation of distribution algorithms, population sizing, model building