Search results for "stuck-open"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
100	Sreejit Chakravarty	A characterization of robust test-pairs for stuck-open faults.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault simulation, robust tests, stuck-open faults, test generation algorithms
91	Zaifu Zhang, Robert D. McLeod, Witold Pedrycz	A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	stuck-open and gate delay faults, Neural networks, test pattern generation
83	Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky	Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
79	Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim	Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits.	DAC	1989	DBLP DOI BibTeX RDF
73	Rene David, S. Rahal, J. L. Rainard	Some relationships between delay testing and stuck-open testing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF	stuck-open, combinational circuits, CMOS, Delay testing, robust test
60	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
57	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
57	Michael Nicolaidis	Shorts in self-checking circuits.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits
54	Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya	CMOS Stuck-open Fault Detection Using Single Test Patterns.	DAC	1989	DBLP DOI BibTeX RDF
51	Michael J. Bryan, Srinivas Devadas, Kurt Keutzer	Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
51	Sarma Sastry, Melvin A. Breuer	Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
49	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detectability of internal bridging faults in scan chains.	ASP-DAC	2009	DBLP DOI BibTeX RDF
49	Feng Shi 0010, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
49	Janusz A. Starzyk, Dong Liu	Locating stuck faults in analog circuits.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
49	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
47	Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou	On Testability of Multiple Precharged Domino Logic.	ISQED	2000	DBLP DOI BibTeX RDF
46	S. Koeppe	Optimal Layout to Avoid CMOS Stuck-Open Faults.	DAC	1987	DBLP DOI BibTeX RDF
44	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of Sequence-Dependent Chips.	VTS	2002	DBLP DOI BibTeX RDF
44	Niraj K. Jha	Multiple Stuck-Open Fault Detection in CMOS Logic Circuits.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	multiple stuck-open fault detection, logic testing, CMOS logic circuits, logic circuits, CMOS integrated circuits, integrated logic circuits, two-pattern tests
42	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.	DFT	2008	DBLP DOI BibTeX RDF
42	Elham K. Moghaddam, Shaahin Hessabi	An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits.	DSD	2007	DBLP DOI BibTeX RDF
42	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
42	Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya	New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.	VLSI Design	1997	DBLP DOI BibTeX RDF
42	Sreejit Chakravarty, S. S. Ravi	Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
42	Sreejit Chakravarty	On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract).	DAC	1990	DBLP DOI BibTeX RDF
42	Beyin Chen, Chung-Len Lee 0001	Universal test set generation for CMOS circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	functional testing, automatic test generation, CMOS circuits, stuck-open faults, universal test set
42	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
40	A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz	Testing complementary pass-transistor logic circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Hyung Ki Lee, Dong Sam Ha	SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	DAC	1990	DBLP DOI BibTeX RDF
39	Malay Kule, Hafizur Rahaman 0001, Bhargab B. Bhattacharya	Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
39	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu	Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
39	Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud	Stuck-open fault diagnosis with stuck-at model.	ETS	2005	DBLP DOI BibTeX RDF
39	Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud	A novel stuck-at based method for transistor stuck-open fault diagnosis.	ITC	2005	DBLP DOI BibTeX RDF
39	François Darlay	Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
39	V. Kim, T. Chen	Assessing SRAM test coverage for sub-micron CMOS technologies.	VTS	1997	DBLP DOI BibTeX RDF	submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
39	Salvador Manich, Michael Nicolaidis, Joan Figueras	Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring.	VTS	1996	DBLP DOI BibTeX RDF	mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness
39	Michele Favalli, Marcello Dalpasso, Piero Olivo	Modeling and simulation of broken connections in CMOS IC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
37	Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou	Testable Designs of Multiple Precharged Domino Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
35	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
35	Sandip Kundu, Sudhakar M. Reddy	Robust tests for parity trees.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	linear gates, parity trees, URTS, robust tests, test length
32	Piotr R. Sidorowicz, Janusz A. Brzozowski	A framework for testing special-purpose memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi	Diagnosing Single Faults for Interconnects in SRAM Based FPGAs.	ASP-DAC	1999	DBLP DOI BibTeX RDF	FPGA, testing, fault diagnosis, fault model
32	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Novel Control Pattern Generators for Interconnect Testing with Boundary Scan.	DFT	1999	DBLP DOI BibTeX RDF	BIST, boundary scan, Interconnect testing
32	Niraj K. Jha	Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
32	Niraj K. Jha	Testing for multiple faults in domino-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
32	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.	ETS	2006	DBLP DOI BibTeX RDF
32	F. Darlay, Bernard Courtois	Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
32	Jhing-Fa Wang, Tah-Yuan Kuo, Jau-Yien Lee	A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits.	DAC	1989	DBLP DOI BibTeX RDF
32	Weiwei Mao, Xieting Ling	Robust test generation algorithm for stuck-open fault in CMOS circuits.	DAC	1986	DBLP DOI BibTeX RDF
32	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An Accumulator-Based BIST Approach for Two-Pattern Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing
32	Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi	On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model.	ICPP	1997	DBLP DOI BibTeX RDF	CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults
32	Meng-Lieh Sheu, Chung-Len Lee 0001	A programmable multiple-sequence generator for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing
27	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Fault Emulation for Dependability Evaluation of VLSI Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	S. M. Aziz, Joarder Kamruzzaman	Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
25	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
25	Jin-Fu Li 0001	Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Jin-Fu Li 0001, Chou-Kun Lin	Modeling and Testing Comparison Faults for Ternary Content Addressable Memories.	VTS	2005	DBLP DOI BibTeX RDF
25	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Testing SRAM-Based Content Addressable Memories.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory
25	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
25	Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man	Design of a C-testable booth multiplier using a realistic fault model.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	test generation, design for testability, fault modelling, Array multipliers, C-testability
25	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
25	Andres R. Takach, Niraj K. Jha	Easily testable gate-level and DCVS multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
25	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modeling and fault equivalence in CMOS technology.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	test generation, Fault modeling, fault collapsing, fault equivalence
25	Dick L. Liu, Edward J. McCluskey	Design of large embedded CMOS PLAs for built-in self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Tsai-Ling Tsai, Jin-Fu Li 0001, Chun-Lung Hsu, Chi-Tien Sun	Testing stuck-open faults of priority address encoder in content addressable memories.	ASP-DAC	2019	DBLP DOI BibTeX RDF
22	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras	Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
22	Adit D. Singh	Cell Aware and stuck-open tests.	ETS	2016	DBLP DOI BibTeX RDF
22	Xijiang Lin, Wu-Tung Cheng, Janusz Rajski	On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.	ATS	2015	DBLP DOI BibTeX RDF
22	Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski	Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits.	VLSID	2015	DBLP DOI BibTeX RDF
22	Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez 0001, Chuck Hawkins, Jaume Segura 0001	Testing of Stuck-Open Faults in Nanometer Technologies.	IEEE Des. Test Comput.	2012	DBLP DOI BibTeX RDF
22	Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai	Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs.	ICCAD	2010	DBLP DOI BibTeX RDF
22	Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz	Multiple fault activation cycle tests for transistor stuck-open faults.	ITC	2010	DBLP DOI BibTeX RDF
22	Roberto Gómez 0001, Víctor H. Champac, Chuck Hawkins, Jaume Segura 0001	A modern look at the CMOS stuck-open fault.	LATW	2009	DBLP DOI BibTeX RDF
22	Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura 0001	Stuck-Open Fault Leakage and Testing in Nanometer Technologies.	VTS	2009	DBLP DOI BibTeX RDF
22	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell.	IEEE Trans. Instrum. Meas.	2008	DBLP DOI BibTeX RDF
22	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu	Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.	ATS	2008	DBLP DOI BibTeX RDF
22	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detection of Internal Stuck-open Faults in Scan Chains.	ITC	2008	DBLP DOI BibTeX RDF
22	Afzel Noore	Improved IDDQ design-for-testability technique to detect CMOS stuck-open faults.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
22	Fadi A. Aloul, Assim Sagahyroon, Bashar Al-Rawi	Exciting Stuck-Open faults in CMOS Circuits Using ILP Techniques.	AICCSA	2006	DBLP DOI BibTeX RDF
22	Afzel Noore	Reliable detection of CMOS stuck-open faults due to variable internal delays.	IEICE Electron. Express	2005	DBLP DOI BibTeX RDF
22	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count.	J. Comput. Sci. Technol.	2002	DBLP DOI BibTeX RDF
22	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Rochit Rajsuman	Testable design of BiCMOS circuits for stuck-open fault detection using single patterns.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
22	Kiyoshi Furuya, Susumu Yamazaki, Masayuki Sato	Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing.	IEICE Trans. Inf. Syst.	1995	DBLP BibTeX RDF
22	Slawomir Pilarski, Kevin James Wiebe	Counter-Based Compaction: Delay and Stuck-Open Faults.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	edge counting, ones counting, transition counting, built-in self-test, Aliasing probability, test response compaction
22	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	Accumulator-based BIST approach for stuck-open and delay fault testing.	ED&TC	1995	DBLP DOI BibTeX RDF
22	Hyung Ki Lee, Dong S. Ha 0001	An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	VLSI Design	1994	DBLP DOI BibTeX RDF
22	Chih-Ang Chen, Sandeep K. Gupta 0001	BIST Test Pattern Generators for Stuck-Open and Delay Testing.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
22	Enrico Macii, Qing Xu	Modeling stuck-open faults in CMOS iterative circuits.	Great Lakes Symposium on VLSI	1993	DBLP DOI BibTeX RDF
22	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya	Testable design for BiCMOS stuck-open fault detection.	VTS	1993	DBLP DOI BibTeX RDF
22	Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita	Stuck-open faults test generation for cmos combinational circuits.	Syst. Comput. Jpn.	1991	DBLP DOI BibTeX RDF
22	Steven D. Millman, Edward J. McCluskey	Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers.	FTCS	1991	DBLP DOI BibTeX RDF
22	Kuen-Jong Lee, Melvin A. Breuer	On the charge sharing problem in CMOS stuck-open fault testing.	ITC	1990	DBLP DOI BibTeX RDF
22	Jerry M. Soden, R. Keith Treece, Michael R. Taylor, Charles F. Hawkins	CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations.	ITC	1989	DBLP DOI BibTeX RDF
22	Henry Cox, Janusz Rajski	Stuck-Open and Transition Fault Testing in CMOS Complex Gates.	ITC	1988	DBLP DOI BibTeX RDF
22	Sudhakar M. Reddy, Madhukar K. Reddy	Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF
22	Madhukar K. Reddy, Sudhakar M. Reddy	Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
22	Gary L. Craig, Charles R. Kime	Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults.	ITC	1985	DBLP BibTeX RDF
22	Yacoub M. El-Ziq, Richard J. Cloutier	Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI.	ITC	1981	DBLP BibTeX RDF
22	Yacoub M. El-Ziq	Automatic test generation for stuck-open faults in CMOS VLSI.	DAC	1981	DBLP BibTeX RDF
22	Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang	IDDT ATPG Based on Ambiguous Delay Assignments.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	IDDT testing, delay Assignments, stuck-open fault