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1993-2002 (19) 2003-2004 (19) 2005 (18) 2006 (29) 2007 (22) 2008 (33) 2009 (23) 2010 (19) 2011 (27) 2012 (28) 2013 (15) 2014 (26) 2015 (23) 2016 (15) 2017 (17) 2018 (19) 2019-2020 (22) 2021-2022 (20) 2023 (7)
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article(127) book(1) inproceedings(271) phdthesis(2)
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Results
Found 401 publication records. Showing 401 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
87Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy 0001 Device optimization for ultra-low power digital sub-threshold operation. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF device optimization, sub-threshold operation, ultra-low power applications
84Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF sub-threshold leakage, CMOS, within-die variation
80Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun A 2.6 µW sub-threshold mixed-signal ECG SoC. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
74Joseph F. Ryan 0002, Jiajing Wang, Benton H. Calhoun Analyzing and modeling process balance for sub-threshold circuit design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF minimum energy operation, process balance, process imbalance, sub-threshold digital circuits, sub-threshold modeling
70Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini Automatic synthesis of near-threshold circuits with fine-grained performance tunability. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
67Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha P. Chandrakasan Sub-threshold design: the challenges of minimizing circuit energy. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low voltage memory, sub-threshold digital circuits, sub-threshold logic, process variations, dynamic voltage scaling
63Basab Datta, Wayne P. Burleson Temperature effects on energy optimization in sub-threshold circuit design. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
63Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul Robust ultra-low power sub-threshold DTMOS logic. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
59Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
58Sudhanshu Khanna, Benton H. Calhoun Serial sub-threshold circuits for ultra-low-power systems. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF bit width, serial systems, leakage, ultra low power, sub-threshold
55Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha Vt balancing and device sizing towards high yield of sub-threshold static logic gates. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF variability, sub-threshold
55Jonggab Kil, Jie Gu 0003, Chris H. Kim A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF capacitive boosting, sub-threshold circuit, clock skew, global interconnect, variation tolerance
52Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne P. Burleson Low-power sub-threshold design of secure physical unclonable functions. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF embedded system security, sub-threshold circuits, RFID, physical unclonable function
50Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri A PLA based asynchronous micropipelining approach for subthreshold circuit design. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF micro-pipelining, asynchronous, PLA, sub-threshold
48Joseph F. Ryan 0002, Benton H. Calhoun Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
48Ik Joon Chang, Jae-Joon Kim, Kaushik Roy 0001 Robust level converter design for sub-threshold logic. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low power circuit design, sub-threshold logic, level converter
46Jonathan Bentwich The duality principle: irreducibility of sub-threshold psychophysical computation to neuronal brain activation. Search on Bibsonomy Synth. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Materialistic reductionism, Duality principle, Body-mind, Binding problem, Computation, Psychophysics, Neuroscience
45Joyce Kwong, Anantha P. Chandrakasan Variation-driven device sizing for minimum energy sub-threshold circuits. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF minimum energy point, sub-threshold circuits, delay model
43Nikhil Jayakumar, Sunil P. Khatri A variation tolerant subthreshold design approach. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF variation-toleran, self-adjusting, body-biasing, sub-threshold
39Armin Wellig, Julien Zory Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Chao Wang 0016, Jun Zhou 0017, Xin Liu 0015, Muthukumaraswamy Annamalai Arasu, Minkyu Je A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation. Search on Bibsonomy A-SSCC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
36Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii Post-layout leakage power minimization based on distributed sleep transistor insertion. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF sub-threshold current, leakage power, sleep transistor
36Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya Design and implementation of a sub-threshold BFSK transmitter. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Mini Nanua, David T. Blaauw Investigating Crosstalk in Sub-Threshold Circuits. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Hendrawan Soeleman, Kaushik Roy 0001 Digital CMOS logic operation in the sub-threshold region. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello New performance/power/area efficient, reliable full adder design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF d3l, reliability, dynamic, full-adder, sub-threshold
33Deyuan Xiao, Gary Chen, Roger Lee, Yung Liu, ChiCheong Shen Planar split dual gate MOSFET. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF novel device, planar split dual gate, tunable sub-threshold swing, MOSFET
29Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu On Composite Leakage Current Maximization. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage
29Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei New technique in design of active rf cmos mixers for low flicker noise and high conversion gain. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 1.cmos mixer, direct conversion receiver, flicker noise, sub-threshold, ota, noise figure
29Geoffrey C.-F. Yeap Leakage current in low standby power and high performance devices: trends and challenges. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
29Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha Statistical noise margin estimation for sub-threshold combinational circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Hushrav Mogal, Kia Bazargan Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Changbo Long, Jinjun Xiong, Yongpan Liu Techniques of Power-gating to Kill Sub-Threshold Leakage. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos, Dimitris K. Papakostas, C. A. Dimitriadis, Stilianos Siskos Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations
23Monica Gupta, Kirti Gupta, Neeta Pandey A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Jiyong Woo, Shimeng Yu Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays. Search on Bibsonomy ISCAS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Shoucai Yuan, Yamei Liu Dual Threshold voltage Domino Adder Design with Pass transistor Logic using standby Switch for Reducing Sub-Threshold Leakage Current. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. Search on Bibsonomy VLSID The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. Search on Bibsonomy CICC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
23Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. Search on Bibsonomy SoCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
23Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy 0001 Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
23Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell 0002 Extending Synchronization from Super-Threshold to Sub-threshold Region. Search on Bibsonomy ASYNC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
23Peter Polácik, Pavol Quittner Asymptotic behavior of threshold and sub-threshold solutions of a semilinear heat equation. Search on Bibsonomy Asymptot. Anal. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Weifeng Lü, Xianlong Chen, Bo Liu, Ziqiang Xie, Mengxue Guo, Mengjie Zhao Comprehensive performance enhancement of a negative-capacitance nanosheet field-effect transistor with a steep sub-threshold swing at the sub-5-nm node. Search on Bibsonomy Microelectron. J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Teruki Someya, Islam A. K. M. Mahfuzul, Takayasu Sakurai, Makoto Takamiya A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage. Search on Bibsonomy CICC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Callum Laurenson, Mehmet R. Yuce, Jean-Michel Redoute A sub 125 nW sub-threshold analog adaptive sampler in 180 nm CMOS. Search on Bibsonomy EMBC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Luca Magnelli, Felice Crupi, Pasquale Corsonello, Giuseppe Iannaccone A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Chutham Sawigun, Dipankar Pal, Andreas Demosthenous A wide-input linear range sub-threshold transconductor for sub-Hz filtering. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
23Yink Khai Teh, Faisal Mohd-Yasin, Florence Choong, Mamun Bin Ibne Reaz Design of adaptive supply voltage for sub-threshold logic based on sub-1 V bandgap reference circuit. Search on Bibsonomy Microelectron. J. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001 Closed-loop modeling of power and temperature profiles of FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF sub-threshold leakage, dynamic power
23Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy 0001 Process variation tolerant SRAM array for ultra low voltage applications. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
23Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
23Hari Ananthan, Chris H. Kim, Kaushik Roy 0001 Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF forward body bias, junction leakage, sub-threshold leakage, process variations
23Chris Hyung-Il Kim, Kaushik Roy 0001 Ultra-low power DLMS adaptive filter for hearing aid applications. Search on Bibsonomy ISLPED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF DLMS adaptive filter, sub-CMOS, sub-pseudo NMOS, sub-threshold operation, parallel architecture
22Hushrav Mogal, Kia Bazargan Microarchitecture floorplanning for sub-threshold leakage reduction. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy 0001 A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
22Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001 Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Amit Agarwal 0001, Kaushik Roy 0001 A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF diode, low leakage cache, SRAM, gate leakage
21Rajiv V. Joshi, Kaushik Roy 0001 Design of Deep Sub-Micron CMOS Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
21R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
21Vinay Agarwal, Sameer R. Sonkusale A PVT independent subthreshold constant-Gm stage for very low frequency applications. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
21Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim Circuit techniques for ultra-low power subthreshold SRAMs. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
21Enrico Macii Leakage power optimization in standard-cell designs. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
21Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown Analysis and Optimization of Enhanced MTCMOS Scheme. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
21Marwan A. Jabri, Stephen Pickard, Philip H. W. Leong, Y. Xie Algorithmic and implementation issues in analog low power learning neural network chips. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
18David T. Blaauw, Anirudh Devgan, Farid N. Najm Leakage power: trends, analysis and avoidance. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Marcia G. Ramos, Sheila S. Hemami Quantifying visual distortion in low-rate wavelet-coded images. Search on Bibsonomy ICIP (3) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
17Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
17Nikhil Jayakumar, Sunil P. Khatri Minimum Energy Near-threshold Network of PLA based Design. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
17Yu Cao, Lawrence T. Clark Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF delay, process variations, variability
16Alex K. Y. Wong, Kong-Pang Pun, Yuan-Ting Zhang, Oliver Chiu-sing Choy An ECG measurement IC using driven-right-leg circuit. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
15Ravindra Kumar Maurya, Rajesh Saha, Brinda Bhowmick Low to high-frequency noise behavior investigation of steeper sub-threshold swing NC-GeFinFET. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Lidan Wang A 6.435-nW, 26.2-ppm/°C hybrid bandgap reference with stacked ΔVGS compensation in sub-threshold region. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Pushkar Praveen, R. K. Singh Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. Search on Bibsonomy ISCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Nitin Sachdeva, Neetu Gupta, Tarun Kumar Sachdeva Analysis of Sub-threshold Leakage Reduction Techniques for High-Speed Low Power VLSI Circuits. Search on Bibsonomy ICCCNT The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Joel Minguet Lopez, Manon Dampfhoffer, Tifenn Hirtzlin, Lucas Reganaz, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Thomas Magis, Catherine Carabasse, Niccolo Castellani, Valentina Meli, Elisa Vianello, Damien Deleruyelle, Jean-Michel Portal, Gabriel Molas, François Andrieu 1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation. Search on Bibsonomy MIXDES The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
15Tanushree Ganguli, Manash Chanda, Angsuman Sarkar Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime. Search on Bibsonomy Comput. Electr. Eng. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Mohammadreza Rasekhi, Emad Ebrahimi, Hamed Aminzadeh 3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Ramneek Sidhu, Mayank Kumar Rai Electronic transport in doped and dielectric inserted MLGNR interconnects: Crosstalk induced delay and stability analyses at sub-threshold regime. Search on Bibsonomy Microelectron. J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Erfan Abbasian, Shilpi Birla, Morteza Gholipour Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM. Search on Bibsonomy Microelectron. J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Dashan Shi, Jia Yuan, Jialu Yin, Yulian Wang, Shushan Qiao A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Ziyue Chen, Yihui Shi, Ao Hu, Jiarui Xu, Guoyi Yu, Chao Wang 0096 A Novel Fold-Back Current Limiting Protection used in Sub-threshold LDO for Wireless Sensor Applications. Search on Bibsonomy ICTA The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Joel Minguet Lopez, François Rummens, Lucas Reganaz, A. Heraud, Tifenn Hirtzlin, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Niccolo Castellani, Valentina Meli, S. Martin, Thomas Magis, Elisa Vianello, C. Sabbione, Damien Deleruyelle, Marc Bocquet, Jean-Michel Portal, Gabriel Molas, François Andrieu 1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing. Search on Bibsonomy IMW The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Yun Liu, Yongliang Chen, Xiaole Cui A Modeling Attack on the Sub-threshold Current Array PUF. Search on Bibsonomy HOST The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet 40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. Search on Bibsonomy VLSID The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
15Ashish Singh, Rajeevan Chandel, Rohit Dhiman Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects. Search on Bibsonomy Integr. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Kamal Hosen, Md. Sherajul Islam, Catherine Stampfl, Jeongwon Park Numerical Analysis of Gate-All-Around HfO2/TiO2/HfO2 High-K Dielectric Based WSe2 NCFET With Reduced Sub-Threshold Swing and High On/Off Ratio. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Kamlesh Singh, José Pineda de Gyvez Twenty Years of Near/Sub-Threshold Design Trends and Enablement. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Monica Gupta, Kirti Gupta, Neeta Pandey A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Mehrzad Karamimanesh, Ebrahim Abiri, Kourosh Hassanli, Mohammad Reza Salehi, Abdolreza Darabi A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Girish Kumar Mekala, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi 0001 Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current. Search on Bibsonomy DATE The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Bojun Hu, Sanfeng Zhang, Xiong Zhou, Zehao Li, Xiangxin Pan, Zhaoming Ding, Qiang Li A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs. Search on Bibsonomy ICECS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Hao Zhang, Weifeng He, Yanan Sun 0003, Mingoo Seok An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. Search on Bibsonomy ISCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
15Fahim ur Rahman, Rajesh Pamula 0001, Visvesh S. Sathe 0001 Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
15Liang Wen, Longmei Nan, Jing Zhang, Chunning Meng, Yan Lu, Shiqian Qi, Jianping Lv, Yuejun Zhang 65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
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open data data released under the ODC-BY 1.0 license