Search results for "synthesis-for-testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
63	Srivaths Ravi 0001, Niraj K. Jha	Test synthesis of systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
62	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel	Enhancing high-level control-flow for improved testability.	ICCAD	1996	DBLP DOI BibTeX RDF	synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
54	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
52	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
52	Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab	Structural and behavioral synthesis for testability techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
48	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
48	Harry Hengster, Bernd Becker 0001	Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.	FTCS	1999	DBLP DOI BibTeX RDF	EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits
48	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers.	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
43	Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken	Manufacturability and Testability Oriented Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
37	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Synthesis-for-testability of controller-datapath pairs that use gated clocks.	DAC	2000	DBLP DOI BibTeX RDF
37	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
37	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel	Testability Insertion in Behavioral Descriptions.	ISSS	1996	DBLP DOI BibTeX RDF	synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
37	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
37	Franco Fummi, Donatella Sciuto, Micaela Serra	Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal
37	Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth	Synthesis for Testability by Two-Clock Control.	VLSI Design	1997	DBLP DOI BibTeX RDF	two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph
37	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
36	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
36	Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal	Finite state machine synthesis with fault tolerant test function.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Design for combinational test generation, finite state machine synthesis, test function embedding, synthesis for testability, fault-tolerant design
29	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.	DATE	1998	DBLP DOI BibTeX RDF	Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
25	Srinivas Devadas, Kurt Keutzer	Synthesis of robust delay-fault-testable circuits: practice.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	Christof Nagel	Synthesis for testability by synthesis controlling.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
22	Meghanad D. Wagh, Chien-In Henry Chen	High-level design synthesis with redundancy removal for high speed testable adders.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
19	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	Chip-Hong Chang, Aijiao Cui	Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
19	Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara	Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.	IEICE Trans. Inf. Syst.	2007	DBLP DOI BibTeX RDF
19	Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth	A synthesis for testability scheme for finite state machines using clock control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
19	Chien-Chung Tsai, Malgorzata Marek-Sadowska	Logic Synthesis for Testability.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	Fixed-Polarity Reed-Muller Forms, Logic synthesis, Testability
19	Kenneth D. Wagner, Sujit Dey	High-Level Synthesis for Testability: A Survey and Perspective.	DAC	1996	DBLP DOI BibTeX RDF
19	Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Synthesis for testability techniques for asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
19	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis for Testability by Sequential Redundancy Removal Using Retiming.	FTCS	1995	DBLP DOI BibTeX RDF
19	Bernd Becker 0001, Rolf Drechsler	Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.	ED&TC	1995	DBLP DOI BibTeX RDF
19	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Synthesis-for-testability using transformations.	ASP-DAC	1995	DBLP DOI BibTeX RDF
19	Irith Pomeranz, Sudhakar M. Reddy	On Synthesis-for-Testability of Combinational Logic Circuits.	DAC	1995	DBLP DOI BibTeX RDF
19	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Irith Pomeranz, Sudhakar M. Reddy	Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.	FTCS	1993	DBLP DOI BibTeX RDF
19	Bernd Becker 0001	Synthesis for Testability: Binary Decision Diagrams.	Informatik	1992	DBLP DOI BibTeX RDF
19	Chung-Hsing Chen, Daniel G. Saab	Behavioral synthesis for testability.	ICCAD	1992	DBLP DOI BibTeX RDF
19	Bernd Becker 0001	Synthesis for Testability: Binary Decision Diagrams.	STACS	1992	DBLP DOI BibTeX RDF	VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures
19	Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Synthesis for Testability Techniques for Asynchronous Circuits.	ICCAD	1991	DBLP DOI BibTeX RDF
19	Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh	Recent progress in synthesis for testability.	VTS	1991	DBLP DOI BibTeX RDF
19	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology.	DAC	1991	DBLP DOI BibTeX RDF
19		A D&T Roundtable: Synthesis for Testability.	IEEE Des. Test Comput.	1990	DBLP BibTeX RDF
19	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential logic synthesis for testability using register-transfer level descriptions.	ITC	1990	DBLP DOI BibTeX RDF
18	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function
18	Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki	Cost/Quality Trade-off in Synthesis for BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	DFT reuse, BIST, synthesis for testability, testability analysis
18	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Integrated test of interacting controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	built-in self-test, register transfer level, synthesis-for-testability
18	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
18	Albrecht P. Stroele	Synthesis for Arithmetic Built-In Self-Tes.	VTS	2000	DBLP DOI BibTeX RDF	test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
18	Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001	Testability of 2-Level AND/EXOR Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	AND/EXOR, 2-level circuits, synthesis for testability, random pattern testability
18	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
18	Frank F. Hsu, Janak H. Patel	Design for Testability Using State Distances.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	state distance, finite-state-machine, design-for-testability, synthesis-for-testability
18	Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri	Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	synthesis for testability (SFT), testable sequential machines, Cellular automata
18	Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara	An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
18	Harry Hengster, Rolf Drechsler, Bernd Becker 0001, Stefan Eckrich, Tonja Pfeiffer	AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	EXOR based synthesis, synthesis for testability, delay optimization
18	Maria J. Avedillo, José M. Quintana, José Luis Huertas	Constrained state assignment of easily testable FSMs.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Finite state machines, synthesis for testability, state assignment
18	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
18	Bernhard Eschermann	Enhancing on-line testability during synthesis.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	BIST, synthesis for testability, control flow checking, controller synthesis
18	Sen-Pin Lin, Charles Njinda, Melvin A. Breuer	Generating a family of testable designs using the BILBO methodology.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	BILBO design system, built-in self-test, test scheduling, synthesis for testability
18	Bernhard Eschermann	An implicitly testable boundary scan TAP controller.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	test controller, BIST, self-test, boundary scan, synthesis for testability, controller design
18	Vishwani D. Agrawal, Kwang-Ting Cheng	Finite state machine synthesis with embedded test function.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	VLSI, Computer-Aided Design, Test Generation, Logic Synthesis, Synthesis for Testability
18	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton	Redundancies and don't cares in sequential logic synthesis.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	redundancies, synthesis for testability, don't cares
14	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Heuristic minimization of Boolean relations using testing techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
11	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Switching activity generation with automated BIST synthesis forperformance testing of interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
11	Vishwani D. Agrawal, Kwang-Ting Cheng	Test Function Specification in Synthesis.	DAC	1990	DBLP DOI BibTeX RDF