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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 38 occurrences of 34 keywords
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Results
Found 48 publication records. Showing 48 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | C. P. Ravikumar, Rahul Kumar |
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
Multi-TAP Controller Architecture for Digital System Chips. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP |
28 | Indradeep Ghosh, Sujit Dey, Niraj K. Jha |
A fast and low-cost testing technique for core-based system-chips. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Yankin Tanurhan |
Processors and FPGAs Quo Vadis? |
Computer |
2006 |
DBLP DOI BibTeX RDF |
Programmable system chips, Embedded computing |
21 | Prab Varma, Sandeep Bhatia |
A structured test re-use methodology for core-based system chips. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
Testing embedded-core based system chips. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Yervant Zorian |
System-Chip Test Strategies (Tutorial). |
DAC |
1998 |
DBLP DOI BibTeX RDF |
system-on-chip test, testing embedded core, intellectual property test |
19 | Prab Varma |
System Chip Test Challenges, Are There Solutions Today? (Panel). |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Erik Jan Marinissen |
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
system chips, test protocol, test protocol scheduling, test generation, expansion, embedded cores |
17 | Iasson Vassiliou, Henry Chang, Alper Demir 0001, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli |
A video driver system designed using a top-down, constraint-driven methodology. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Analog CAD, Video Driver System Chips, Analog Behavioral Modeling, Design Methodologies |
14 | Yong-Xiao Chen, Jin-Fu Li 0001 |
Testing of Non-volatile Logic-Based System Chips. |
ATS |
2014 |
DBLP DOI BibTeX RDF |
|
14 | W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang |
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. |
IET Comput. Digit. Tech. |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips |
CoRR |
2007 |
DBLP BibTeX RDF |
|
14 | Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park |
An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing |
14 | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains |
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
TAM and wrapper design, test scheduling, SOC-test |
14 | Tom Waayers |
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
A novel test time reduction algorithm for test architecture design for core-based system chips. |
ETW |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Data invalidation analysis for scan-based debug on multiple-clock system chips. |
ETW |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Mohsen Nahvi, André Ivanov |
A packet switching communication-based test access mechanism for system chips. |
ETW |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Erik Jan Marinissen, Yervant Zorian |
Testing Embedded Core-Based System Chips. |
LATW |
2001 |
DBLP BibTeX RDF |
|
14 | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
Testing Embedded-Core-Based System Chips. |
Computer |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001 |
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
Core-Based Scan Architecture for Silicon Debug. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Érika F. Cota, Chunsheng Liu |
Constraint-Driven Test Scheduling for NoC-Based Systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
7 | A. Richard Newton |
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
7 | Kwang-Ting (Tim) Cheng |
Cocktail approach to functional verification. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
validation, functional verification, multiprocessor SoC, SiP, BISR |
7 | Shyue-Kung Lu, Shih-Chang Huang |
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. |
MTDT |
2004 |
DBLP DOI BibTeX RDF |
|
7 | YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang 0001 |
A New Maximal Diagnosis Algorithm for Bus-structured Systems. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
7 | Greg Stitt, Frank Vahid |
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. |
IEEE Des. Test Comput. |
2002 |
DBLP DOI BibTeX RDF |
|
7 | C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma |
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
6 | Erik Jan Marinissen, Yervant Zorian |
Guest Editors' Introduction: The Status of IEEE Std 1500. |
IEEE Des. Test Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Kwang-Ting (Tim) Cheng |
Supporting cost-effective innovation. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
nanoscale, variability, IR drop, power supply noise |
6 | Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez |
Testing and Diagnosis of Power Switches in SOCs. |
ETS |
2006 |
DBLP DOI BibTeX RDF |
|
6 | Rajesh K. Gupta 0001 |
Driving Research in System-Chip Design Technology. |
Computer |
2003 |
DBLP DOI BibTeX RDF |
|
6 | Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
march test algorithm, memory diagnostics, BIST, memory testing, CAM |
6 | Sandeep Kumar Goel, Erik Jan Marinissen |
SOC test architecture design for efficient utilization of test bandwidth. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization |
6 | Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian |
On IEEE P1500's Standard for Embedded Core Test. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
core test wrapper, core test language, compliance levels, standardization, embedded cores |
6 | Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta 0001 |
Structured Component Composition Frameworks for Embedded System Design. |
HiPC |
2002 |
DBLP DOI BibTeX RDF |
|
6 | Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin |
Test Scheduling of BISTed Memory Cores for SOC. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
6 | Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosing Embedded Content Addressable Memories. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
6 | Juha-Pekka Soininen, Sandrine Boumard, Tommi Salminen, Hannu Heusala |
Application of Decision-Making Method for Architecture Selection of ADSL Modem. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Yervant Zorian, Erik Jan Marinissen |
System chip test: how will it impact your design? |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
6 | S. J. Krolikoski, Frank Schirrmeister, B. Salefski, J. Rowson, Grant Martin |
Methodology and technology for virtual component driven hardware/software co-design on the system-level. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
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