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Searching for phrase system-chips (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996-2002 (27) 2003-2007 (18) 2009-2014 (3)
Publication types (Num. hits)
article(18) inproceedings(30)
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The graphs summarize 38 occurrences of 34 keywords

Results
Found 48 publication records. Showing 48 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
33C. P. Ravikumar, Rahul Kumar Divide-and-Conquer IDDQ Testing for Core-Based System Chips. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Bart Vermeulen, Tom Waayers, Sjaak Bakker Multi-TAP Controller Architecture for Digital System Chips. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP
28Indradeep Ghosh, Sujit Dey, Niraj K. Jha A fast and low-cost testing technique for core-based system-chips. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23Yankin Tanurhan Processors and FPGAs Quo Vadis? Search on Bibsonomy Computer The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Programmable system chips, Embedded computing
21Prab Varma, Sandeep Bhatia A structured test re-use methodology for core-based system chips. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
21Yervant Zorian, Erik Jan Marinissen, Sujit Dey Testing embedded-core based system chips. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
19Yervant Zorian System-Chip Test Strategies (Tutorial). Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF system-on-chip test, testing embedded core, intellectual property test
19Prab Varma System Chip Test Challenges, Are There Solutions Today? (Panel). Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
17Erik Jan Marinissen The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF system chips, test protocol, test protocol scheduling, test generation, expansion, embedded cores
17Iasson Vassiliou, Henry Chang, Alper Demir 0001, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli A video driver system designed using a top-down, constraint-driven methodology. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Analog CAD, Video Driver System Chips, Analog Behavioral Modeling, Design Methodologies
14Yong-Xiao Chen, Jin-Fu Li 0001 Testing of Non-volatile Logic-Based System Chips. Search on Bibsonomy ATS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
14W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Erik Jan Marinissen On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips Search on Bibsonomy CoRR The full citation details ... 2007 DBLP  BibTeX  RDF
14Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
14Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Erik Jan Marinissen On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Bart Vermeulen Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
14Sandeep Kumar Goel, Erik Jan Marinissen A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF TAM and wrapper design, test scheduling, SOC-test
14Tom Waayers An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Erik Jan Marinissen A novel test time reduction algorithm for test architecture design for core-based system chips. Search on Bibsonomy ETW The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Bart Vermeulen Data invalidation analysis for scan-based debug on multiple-clock system chips. Search on Bibsonomy ETW The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
14Sandeep Kumar Goel, Bart Vermeulen Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
14Bart Vermeulen, Tom Waayers, Sjaak Bakker EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
14Mohsen Nahvi, André Ivanov A packet switching communication-based test access mechanism for system chips. Search on Bibsonomy ETW The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
14Erik Jan Marinissen, Yervant Zorian Testing Embedded Core-Based System Chips. Search on Bibsonomy LATW The full citation details ... 2001 DBLP  BibTeX  RDF
14Yervant Zorian, Erik Jan Marinissen, Sujit Dey Testing Embedded-Core-Based System Chips. Search on Bibsonomy Computer The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
14Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001 Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
13Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel Core-Based Scan Architecture for Silicon Debug. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
7Érika F. Cota, Chunsheng Liu Constraint-Driven Test Scheduling for NoC-Based Systems. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7A. Richard Newton Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
7Kwang-Ting (Tim) Cheng Cocktail approach to functional verification. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF validation, functional verification, multiprocessor SoC, SiP, BISR
7Shyue-Kung Lu, Shih-Chang Huang Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. Search on Bibsonomy MTDT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang 0001 A New Maximal Diagnosis Algorithm for Bus-structured Systems. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
7Greg Stitt, Frank Vahid Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
7C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
6Erik Jan Marinissen, Yervant Zorian Guest Editors' Introduction: The Status of IEEE Std 1500. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
6Kwang-Ting (Tim) Cheng Supporting cost-effective innovation. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF nanoscale, variability, IR drop, power supply noise
6Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez Testing and Diagnosis of Power Switches in SOCs. Search on Bibsonomy ETS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
6Rajesh K. Gupta 0001 Driving Research in System-Chip Design Technology. Search on Bibsonomy Computer The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
6Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF march test algorithm, memory diagnostics, BIST, memory testing, CAM
6Sandeep Kumar Goel, Erik Jan Marinissen SOC test architecture design for efficient utilization of test bandwidth. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization
6Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian On IEEE P1500's Standard for Embedded Core Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF core test wrapper, core test language, compliance levels, standardization, embedded cores
6Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta 0001 Structured Component Composition Frameworks for Embedded System Design. Search on Bibsonomy HiPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
6Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin Test Scheduling of BISTed Memory Cores for SOC. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
6Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu Testing and Diagnosing Embedded Content Addressable Memories. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
6Juha-Pekka Soininen, Sandrine Boumard, Tommi Salminen, Hannu Heusala Application of Decision-Making Method for Architecture Selection of ADSL Modem. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
6Yervant Zorian, Erik Jan Marinissen System chip test: how will it impact your design? Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
6S. J. Krolikoski, Frank Schirrmeister, B. Salefski, J. Rowson, Grant Martin Methodology and technology for virtual component driven hardware/software co-design on the system-level. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
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