Search results for "systolic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Jae-Jin Lee, Gi-Yong Song	Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.	FPGA	2004	DBLP DOI BibTeX RDF
92	Nam Ling, Magdy A. Bayoumi	Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
88	Oscar H. Ibarra, Stephen M. Sohn	On Mapping Systolic Algorithms onto the Hypercube.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
84	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
80	Hyesook Lim, Earl E. Swartzlander Jr.	An efficient systolic array for the discrete cosine transform based on prime-factor decomposition .	ICCD	1995	DBLP DOI BibTeX RDF	prime-factor decomposition, index mappings, VLSI, discrete cosine transforms, discrete cosine transform, systolic arrays, systolic array, VLSI implementation, array signal processing
76	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
76	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
75	Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas	Translating systolic arrays into instruction systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE
72	Jae-Jin Lee, Gi-Yong Song	Super Semi-systolic Array-Based Application-Specific PLD Architecture.	ARC	2006	DBLP DOI BibTeX RDF
72	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Area efficient computing structures for concurrent error detection in systolic arrays.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
72	Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong	Systematic generation of linear allocation functions in systolic array design.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
72	G. A. Frank, E. M. Greenawalt, A. V. Kulkarni	A systolic processor for signal processing.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
67	Soonhak Kwon, Chang Kim, Chun Pyo Hong	Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2m) Using LSB First Algorithm.	WILF	2005	DBLP DOI BibTeX RDF	LSB first algorithm, VLSI, finite field, Systolic array, data flow, fault tolerant architecture
67	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
67	E. Pascal Gribomont, Vincent Van Dongen	Generic Systolic Arrays: A Methodology for Systolic Design.	TAPSOFT	1993	DBLP DOI BibTeX RDF
64	Vamsi Krishna, Abdel Ejnioui, N. Ranganathan	A tree matching chip.	VLSI Design	1996	DBLP DOI BibTeX RDF	tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture
63	Hartmut Schmeck, Heiko Schröder 0001	Dictionary Machines for Different Models of VLSI.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine
63	Vwani P. Roychowdhury, Thomas Kailath	Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
63	Nikolay Petkov Turkedjiev	Synthesis of Systolic Algorithms and Processor Arrays.	CONPAR	1986	DBLP DOI BibTeX RDF
63	Earl E. Swartzlander Jr.	Systolic FFT Processors: A Personal Perspective.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms
59	M. Ch. Karra, M. P. Bekakos	A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	FPGA technology, parallelism, finite-state machine, time complexity, systolic arrays, processing elements
59	Nuha A. S. Alwan	A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Trigonometric series, sinusoidal sequence generation, pipelining, systolic arrays
59	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2m) for High Speed Cryptographic Processors.	ICCSA (1)	2005	DBLP DOI BibTeX RDF	VLSI, finite field, systolic array, irreducible trinomial
59	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	A Linear Systolic Array for Multiplication in GF(2m) for High Speed Cryptographic Processors.	ICCSA (4)	2004	DBLP DOI BibTeX RDF	Riemann Hypothesis, Artins conjecture for primitive roots, systolic array, Finite field multiplier, all one polynomial
59	Chin-Liang Wang, Jyh-Huei Guo	New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m).	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	finite field division, finite field inversion, parallel-in parallel-out architecture, VLSI, systolic array, Finite field arithmetic
59	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
59	Nuha A. S. Alwan	Systematic Design of Systolic Correlators with Application to Parallel Blackman-Tukey Spectral Estimation.	Computing	2001	DBLP DOI BibTeX RDF	Blackman, Tukey spectral estimation, systematic design of systolic arrays, systolic correlators, systolic DFT
59	Abdel Ejnioui, N. Ranganathan	Systolic algorithms for tree pattern matching.	ICCD	1995	DBLP DOI BibTeX RDF	pattern tree, subject tree, PRAM model of computation, linear systolic array model, parallel algorithms, parallel algorithms, pattern matching, systolic arrays, SIMD machine, systolic algorithms, tree pattern matching
55	Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
55	Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments.	SCCC	2003	DBLP DOI BibTeX RDF	Reconfigurable Systolic Arrays, Fast Fourier Transform, Rewriting-Logic, Term Rewriting Systems
55	Eric M. Dowling, Zuqiang Fu, Ron S. Drafz	HARP: An Open Architecture for Parallel Matrix and Signal Processing.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	HARP, matrix processing, Hybrid Array RingProcessor, memory mapped processing cells, open backplane, bidirectional systolic ring, bus controller, DMA function, systolic communication, reduced overhead message passing, digital signalprocessor, systolicarray, parallel algorithms, parallel, parallel architectures, multiprocessor, shared memory, signal processing, signal processing, systolic arrays, shared memory systems, interprocessor communication, open architecture, Application specific architecture
55	Karl-Heinz Zimmermann	A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
55	Nam Ling	A special purpose formal verifier for systolic designs in DSP applications.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
55	Monica Lam 0001	Compiler Optimizations for Asynchronous Systolic Array Programs.	POPL	1988	DBLP DOI BibTeX RDF
54	Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.	Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT.	ASAP	1996	DBLP DOI BibTeX RDF	finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors
54	V. Visvanathan, S. Ramanathan	A modular systolic architecture for delayed least mean squares adaptive filtering.	VLSI Design	1995	DBLP DOI BibTeX RDF	modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods
54	Chris J. Scheiman, Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Transitive Closure.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure
51	Moha'med O. Al-Jaafreh, Adel Ali Al-Jumaily	Type-2 Fuzzy System Based Blood Pressure Parameters Estimation.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Type-2 Fuzzy System, photo-plethysmography, Heart rate, Blood Pressure
50	Risto Honkanen	Systolic Routing in an Optical Fat Tree.	ISPA	2005	DBLP DOI BibTeX RDF	Optical fat tree, systolic routing, work-optimal routing
50	Chien-Hsing Wu 0002, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang	High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division
50	Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, Hiecheol Kim	A New Systolic Array for Least Significant Digit First Multiplication in GF(2m).	ICCSA (3)	2004	DBLP DOI BibTeX RDF	Digit-Serial Architecture, VLSI, Cryptography, Systolic Array, Finite Field Multiplication
50	Pol-Lin Tai, Chii-Tung Liu, Jia-Shung Wang	An Integrated Systolic Array Design for Video Compression.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	integrated systolic design, wavelet transform, vector quantization, block-matching
50	Soonhak Kwon	Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields.	ICICS	2002	DBLP DOI BibTeX RDF	systolic multiplier, finite field, basis, all one polynomial
50	Fikret Erçal, Mark Allen, Hao Feng 0001	A Systolic Image Difference Algorithm for RLE-Compressed Images.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	image compression, run-length encoding, Systolic algorithm, image difference
50	Yen-Chun Lin, Jyh-Chian Chen	An Efficient Systolic Algorithm for the Longest Common Subsequence Problem.	J. Supercomput.	1998	DBLP DOI BibTeX RDF	parallel algorithm, VLSI, systolic array, multicomputer, Longest common subsequence
50	Peter Kornerup	A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
50	Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza	A Systolic Redundant Residue Arithmetic Error Correction Circuit.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	systolic redundant residue arithmetic error correction circuit, concurrent fault tolerance capability, redundant residue number system, high speed VLSI circuit realization, parallel systolic architecture, parallel algorithms, VLSI, systolic arrays, digital arithmetic, error correction, real-time applications, error recovery, decision table, processing element, transient errors, residue arithmetic, memory element
50	Paul S. Lewis, Sun-Yuan Kung	An Optimal Systolic Array for the Algebraic Path Problem.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	optimal systolic array, orthogonally connected processing elements, systolic implementation, logic design, systolic arrays, processing elements, algebraic path problem
50	Rami G. Melhem	A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement
47	Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein	Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic.	SBCCI	2004	DBLP DOI BibTeX RDF	configware, morphware, reconfigurable systolic arrays, term rewriting systems (TRS), dynamic programming, rewriting-logic
47	Rumen Andonov, Sanjay V. Rajopadhye	Knapsack on VLSI: from Algorithm to Optimal Circuit.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays
46	Antonio E. de la Serna	Differential Scoring for Systolic Sequence Alignment.	BIBE	2007	DBLP DOI BibTeX RDF
46	Kentaro Sano, Takanori Iizuka, Satoru Yamamoto	Systolic Architecture for Computational Fluid Dynamics on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
46	Yun Yang, Wenqing Zhao, Yasuaki Inoue	High-performance systolic arrays for band matrix multiplication.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
46	Gloria Martínez, Germán Fabregat, Vicente Hernández	Solving the Generalized Sylvester Equation with a Systolic Library.	VECPAR	2000	DBLP DOI BibTeX RDF
46	Fikret Erçal, Mark Allen, Hao Feng 0001	A Systolic Algorithm to Process Compressed Binary Images.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
46	Bertil Schmidt, Manfred Schimmler, Heiko Schröder 0001	Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography.	Euro-Par	1998	DBLP DOI BibTeX RDF
46	Lynn M. Stauffer, Daniel S. Hirschberg	Systolic Self-Organizing Lists Under Transpose.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
46	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili	Design techniques for fault-tolerant systolic arrays.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
46	Cheng-Wen Wu, Ming-Kwang Chang	Bit-level systolic arrays for finite-field multiplications.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
46	Angelo Monti, Adriano Peron	Systolic Tree Omega-Languages.	STACS	1995	DBLP DOI BibTeX RDF
46	Marc Moonen	Implementing the square-root information Kalman filter on a Jacobi-type systolic array.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
46	José L. Hueso, Gloria Martínez, Vicente Hernández	A systolic algorithm for the triangular Stein equation.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
46	Tatyana D. Roziner, Mark G. Karpovsky	Multidimensional fourier transforms by systolic architectures.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
46	Xiaoxiong Zhong, Sanjay V. Rajopadhye	Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions.	PARLE (1)	1991	DBLP DOI BibTeX RDF
46	Norihiko Yoshida	Transformational Derivation of Systolic Arrays.	Concurrency: Theory, Language, And Architecture	1989	DBLP DOI BibTeX RDF
46	Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero	Systematic Hardware Adaptation of Systolic Algorithms.	ISCA	1989	DBLP DOI BibTeX RDF
46	Shek-Wayne Chan, Chin-Long Wey	The design of concurrent error diagnosable systolic arrays for band matrix multiplications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
46	Anup B. Sharma, Keith R. Allen, Roy P. Pargas	Some new systolic designs for two-dimensional convolution.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE, SAGE
46	David Y. Y. Yun, Y. Yun, Chang Nian Zhang	Formal verification of systolic networks using theorem proving techniques (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
46	Chua-Huang Huang, Christian Lengauer	An Implemented Method for Incremmental Systolic Design.	PARLE (1)	1987	DBLP DOI BibTeX RDF
46	Yves Robert	Systolic Algorithms for Path- Finding Problems.	Automata Networks	1986	DBLP DOI BibTeX RDF
46	A. A. Abdel Kader	OCSAMO - A Systolic Array for Matrix Operations.	CONPAR	1986	DBLP DOI BibTeX RDF
46	Tudor Jebelean	Design of a systolic coprocessor for rational addition.	ASAP	1995	DBLP DOI BibTeX RDF	systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD
46	Judith O. Berkey, Pearl Y. Wang	A Systolic-Based Parallel Bin Packing Algorithm.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	systolic-based parallel bin packing algorithm, asymptotic error bound, execution performance, serial algorithms, parallel algorithms, computational complexity, approximation algorithm, parallelizations, time complexity, systolic arrays, operations research
46	Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product
46	Christian Lengauer, Jingling Xue	A systolic array for pyramidal algorithms.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	pyramid node linking, systolic design, image processing, image segmentation, systolic array
42	Sudhir Vinjamuri, Viktor K. Prasanna	Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors.	PaCT	2009	DBLP DOI BibTeX RDF	systolic array designs, parallel programming, high performance computing, multicore, dependency graphs
42	Chiou-Yng Lee, Che Wun Chiou	New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	finite field, normal basis, polynomial basis, bit-parallel systolic multiplier
42	Kung Yao, Flavio Lorenzelli	Systolic Algorithms and Architectures for High-Throughput Processing Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	recursive least-squares estimation, Kalman filtering, systolic array, linear algebra, QR decomposition, least-squares estimation
42	Emina I. Milovanovic, Igor Z. Milovanovic, Michael P. Bekakos, I. N. Tselepis	Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	FPGA, Parallel computations, Systolic arrays, All-pairs shortest paths, Parallel iterative methods
42	Yunbi Chen, Jingsong He	Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression.	ICES	2007	DBLP DOI BibTeX RDF	Image Compression, Systolic Array, Evolvable Hardware, Fitness Evaluation
42	Ting Qin, Haitao Zhang, Zonghai Chen, Wei Xiang	Continuous CMAC-QRLS and Its Systolic Array.	Neural Process. Lett.	2005	DBLP DOI BibTeX RDF	CMAC-QRLS, systolic array, B-splines, QR decomposition
42	Amir K. Daneshbeh, M. Anwarul Hasan	A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm
42	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu	Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
42	A. Chorevas, Dionysios I. Reisis	Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	VLSI, FIR filter, systolic architectures, QAM
42	Sek M. Chai, D. Scott Wills	Systolic Opportunities for Multidimensional Data Streams.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	area I/O, design and performance evaluation, systolic arrays, parallel computer architecture
42	J. H. Weston, Chang N. Zhang, Hua Li	Some Space Considerations of VLSI Systolic Array Mappings.	ICPADS	2000	DBLP DOI BibTeX RDF	nested loop algorithm, systolic array, matrix, processing element, space-time mapping
42	Jean Frédéric Myoupo, Anne-Cécile Fabret	A Modular Systolic Linearization of the Warshall-Floyd Algorithm.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	Modular linear systolic algorithms, shortest path, matrix multiplication, transitive closure
42	Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller	A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs.	ISMVL	1996	DBLP DOI BibTeX RDF	neuron MOSFET, product sum computation, systolic array, Ternary logic
42	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
42	Catherine Mongenet, Guy-René Perrin	Synthesis of Systolic arrays for Inductive Problems.	PARLE (1)	1987	DBLP DOI BibTeX RDF	synthesis, systolic arrays
41	I. M. Bland, Graham M. Megson	The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology.	FCCM	1998	DBLP DOI BibTeX RDF
38	Lejla Batina, Geeke Muurling	Montgomery in Practice: How to Do It More Efficiently in Hardware.	CT-RSA	2002	DBLP DOI BibTeX RDF	scalability, performance model, systolic array, Montgomery multiplication, modular exponentiation
38	Vera P. Behar, Christo A. Kabakchiev, Lyubka Doukovska	Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	CFAR API processor, detection in pulse jamming, target detection performance calculation, parallel algorithms, systolic architecture
38	J. G. Liu 0001, Francis H. Y. Chan, Francis K. Lam, Hon Fung Li	A Novel Approach to Fast Discrete Hartley Transform.	ISPAN	1999	DBLP DOI BibTeX RDF	Hartley transform, parallel processing, systolic array, moment, fast transform
38	Jean Frédéric Myoupo	A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems.	ICCI	1991	DBLP DOI BibTeX RDF	Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays
38	Alexandre Abellard, Patrick Abellard	A Design Methodology of Systolic Architectures Based on a Petri Net Extension. Application to a Stereovision Hardware/Software Processing Improvement.	ICSEA	2008	DBLP DOI BibTeX RDF
38	A. Neslin Ismailoglu, Murat Askar	SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.	DSD	2008	DBLP DOI BibTeX RDF
38	Laura Ruff	Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays.	SYNASC	2007	DBLP DOI BibTeX RDF