Search results for "tdc"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
130	Yifei Luo, Gang Chen, Kuan Zhou	A picosecond TDC architecture for multiphase PLLs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc
124	Xiaowen Kang, Yaqiang Liu, Xishan Sun, Shi Wang, Yan Xia, Zhicheng Zhang, Zhaoxia Wu, Yongjie Jin	Front-end Electronics Design based on Vernier Method for a High Resolution MicroPET.	BMEI (2)	2008	DBLP DOI BibTeX RDF	Time-to-Digital Convertor(TDC), Front-end electronics Vernier method, ADC, positron emission tomography(PET), TDC
96	V. Ramakrishnan, Poras T. Balsara	A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter.	VLSI Design	2006	DBLP DOI BibTeX RDF	Time to digital converters, phase detectors, Vernier delay line, TDC
79	Claudio Favi, Edoardo Charbon	A 17ps time-to-digital converter implemented in 65nm FPGA technology.	FPGA	2009	DBLP DOI BibTeX RDF	65nm fpga, deep sub-nanosecond time resolution, high-speed readout, time-correlated instrumentation, time-to-digital converters, ultra-fast digital electronics, optical communications, tdc
68	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
66	Masoud Nikravesh	Concept-based search and questionnaire systems.	Soft Comput.	2008	DBLP DOI BibTeX RDF	PNL, NeuSearch, Z(n)-compact, BISC-DSS, Semantic Web, Fuzzy query, Fuzzy search
66	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Test data compression and TAM design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
66	Masoud Nikravesh	Concept-Based Questionnaire System.	IFSA (2)	2007	DBLP DOI BibTeX RDF
66	Peter M. Levine, Gordon W. Roberts	A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme.	ITC	2004	DBLP DOI BibTeX RDF
51	Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho	A register controlled delay locked loop using a TDC and a new fine delay line scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
50	Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi 0001, Nobukazu Takai, Masao Hotta	A Time-to-Digital Converter with small circuitry.	ASP-DAC	2009	DBLP DOI BibTeX RDF
50	Yasutoshi Makino, Hiroyuki Shinoda	Comfortable Wristband Interface Measuring Myoelectric Pattern.	WHC	2007	DBLP DOI BibTeX RDF
50	Roman Jarina, Michal Kuba, Martin Paralic	Compact Representation of Speech Using 2-D Cepstrum - An Application to Slovak Digits Recognition.	TSD	2005	DBLP DOI BibTeX RDF
50	Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici	Test Data Compression: The System Integrator's Perspective.	DATE	2003	DBLP DOI BibTeX RDF
50	Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao	A high-resolution and fast-conversion time-to-digital converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
50	Elvi Räisänen-Ruotsalainen, Timo Rahkonen, Juha Kostamovaara	A BiCMOS time-to-digital converter with 30 ps resolution.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
50	Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara	A high resolution digital CMOS time-to-digital converter based on nested delay locked loops.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
50	Jan Jonsson, Jonas Vasell	A Comparative Study of Methods for Time-Deterministic Message Delivery in a Multiprocessor Architecture.	IPPS	1996	DBLP DOI BibTeX RDF	Time-deterministic communication, point-to-point interconnection networks, link contention analysis, implementation cost, multiprocessor architectures, communication scheduling, real-time channels
50	Andreas Erzmann, M. Hadeler, Christian Müller-Schloer	A Model for Efficient Programming of Dynamic Applications on Distributed Memory Multiprocessors.	Euro-Par	1995	DBLP DOI BibTeX RDF	Programming Model, Dynamic Load Balancing, Block Matching, Distributed Memory Multiprocessors
36	Abdelrahman G. Habib, Mohamed Dessouky	A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector.	SOCC	2022	DBLP DOI BibTeX RDF
36	Jinyuan Wu, Jingjing Xu	A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage Applications.	EBCCSP	2019	DBLP DOI BibTeX RDF
36	Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho	A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
33	Andrea Esuli, Fabrizio Sebastiani 0001	Training Data Cleaning for Text Classification.	ICTIR	2009	DBLP DOI BibTeX RDF
33	Jean-Paul Deveaux, Andrew Rau-Chaplin, Norbert Zeh	Adaptive Tuple Differential Coding.	DEXA	2007	DBLP DOI BibTeX RDF
33	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell 0002	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
33	Sangho Shin, Kwyro Lee, Sung-Mo Kang	2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop.	ISCAS	2006	DBLP DOI BibTeX RDF
33	Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang	On-chip accumulated jitter measurement for phase-locked loops.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	Wenbo Liu, Hanqing Xing, Le Jin, Randall L. Geiger, Degang Chen 0001	A test strategy for time-to-digital converters using dynamic element matching and dithering.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
33	Mhand Hifi	Dynamic Programming and Hill-Climbing Techniques for Constrained Two-Dimensional Cutting Stock Problems.	J. Comb. Optim.	2004	DBLP DOI BibTeX RDF	dynamic programming, heuristics, hill-climbing, depth-first search, knapsacking, cutting stock
33	Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang	Timing measurement unit with multi-stage TVC for embedded memories.	ASP-DAC	2004	DBLP DOI BibTeX RDF
33	Bryan Nelson, Mani Soma	On-chip calibration technique for delay line based BIST jitter measurement.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Hongzhi Liang, Shubin Liu, Ruixue Ding, Yi Shen 0007, Dengquan Li, Zhangming Zhu	A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
18	Tim Lauber, Lantao Wang, Johannes Bastl, Kenny Vohl, Ralf Wunderlich, Stefan Heinen	A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
18	Xinquan Lai, Mingming Liu, Chen Liu	A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
18	Su-Hyun Han 0001, Seonghyeok Park, Jung-Hoon Chun, Jaehyuk Choi 0001, Seong-Jin Kim	6.7 A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted In- Pixel Histogramming TDC Based on Self-Referenced SAR ADC.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Tim Bruylants, Ben Runyan, Jean-Baptise Lorent	The TDC profile of JPEG XS 3rd edition: new perspectives for graphics content, eSport production, and remote collaboration in low latency.	MHV	2024	DBLP DOI BibTeX RDF
18	Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung	Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS.	VLSID	2024	DBLP DOI BibTeX RDF
18	Menghan Guo, Shoushun Chen, Zhe Gao, Wenlei Yang, Peter Bartkovjak, Qing Qin, Xiaoqin Hu, Dahai Zhou, Qiping Huang, Masayuki Uchiyama, Yoshiharu Kudo, Shimpei Fukuoka, Chengcheng Xu, Hiroaki Ebihara, Xueqing Wang, Peiwen Jiang, Bo Jiang, Bo Mu, Huan Chen, Jason Yang, TJ Dai, Andreas Suess	A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull	A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Haoyi Zhao, Fa Foster Dai	A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Abdelrahman G. Habib, Mohamed Dessouky, Ahmed Naguib	A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Moisés Arredondo-Velázquez, Lucio Fidel Rebolledo-Herrera, Heber Zepeda-Fernández, Eduardo Moreno-Barbosa	Trimmed-TDL-Based TDC Architecture for Time-of-Flight Measurements Tested on a Cyclone V FPGA.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
18	Van Nhan Nguyen, Jong-Wook Lee	A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
18	Ke Cui, Jintao Yu, Jiaxuan Zou, Xiangyu Li 0005	A High-Resolution TDC Design Based on Multistep Fine Time Measurement by Utilizing Delay-Adjustable Looped Carry Chains on FPGAs.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
18	Jin Hu 0006, Dong Li, Xiayu Wang, Rui Ma 0007, Yang Liu 0106, Zhangming Zhu	A 40-ps Resolution Robust Continuous Running VCRO-Based TDC for LiDAR Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Chengcheng Zhang, Ang Hu, Dongsheng Liu, Shuo Ma, Hao Li, Zirui Jin, Jianwei Liu, Yan Wang, Wentao Yang	A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
18	Colin O'Flynn	PicoEMP: A Low-Cost EMFI Platform Compared to BBI and Voltage Fault Injection using TDC and External VCC Measurements.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
18	Zhijie Chen, Xiaoyu Zhang, Yongkuo Ma, Xitong Liang, Xinyu Du, Peiyuan Wan	A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
18	Daniel Junehee Lee, Fei Yuan 0005, Yushi Zhou	A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC.	MWSCAS	2023	DBLP DOI BibTeX RDF
18	Ziqi Wang, Zhongtao Shen, Junchen Wang, Wenhao Dong, Changqing Feng, Shubin Liu	A High Integrative Frequency Measurement Method Based on TDC.	I2MTC	2023	DBLP DOI BibTeX RDF
18	Yanxian Zhou, Donghang Wang, Zerong Hu, Khawaja Qasim Maqbool, Xianbo Li	A 120-dB Dynamic-Range, 24-ps-to-781-ps Resolution Reconfigurable Cyclic TDC Based on a 2× Time Amplifier for LiDAR Applications.	ICTA	2023	DBLP DOI BibTeX RDF
18	Nannan Li, Zhengbo Huang, Jie Zhang 0039, Quan Sun, Jian Luo, Xiaofei Wang	A 9 b 4 GS/s Time-Domain ADC with Self-Reset VTC and Switched-RO TDC Including 8x Hybrid Interpolation.	ICTA	2023	DBLP DOI BibTeX RDF
18	Hao Deng 0003, Phaneendra Bikkina, Esko Mikkola, Runxi Zhang, Jinghong Chen	A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.	ESSCIRC	2023	DBLP DOI BibTeX RDF
18	Na Hyun Kim, Dong-Gyu Kim, Kang Yoon Lee	A Design of High Resolution ADC-Assisted Gated-Ring Oscillator TDC with Digital Calibration.	ICTC	2023	DBLP DOI BibTeX RDF
18	Daniel Junehee Lee, Fei Yuan, Yushi Zhou	Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC.	NEWCAS	2023	DBLP DOI BibTeX RDF
18	Shiyu Su, Oiaochu Zhang, Mike Shuo-Wei Chen	A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC.	CICC	2023	DBLP DOI BibTeX RDF
18	Menghan Guo, Shoushun Chen, Zhe Gao, Wenlei Yang, Peter Bartkovjak, Qing Qin, Xiaoqin Hu, Dahei Zhou, Masayuki Uchiyama, Shimpei Fukuoka, Chengcheng Xu, Hiroaki Ebihara, Andy Wang, Peiwen Jiang, Bo Jiang, Bo Mu, Huan Chen, Jason Yang, TJ Dai, Andreas Suess, Yoshiharu Kudo	A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1 MPixel EVS with 4.6GEvent/s Readout, In-Pixel TDC and On-Chip ISP and ESP Function.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Colin O'Flynn	PicoEMP: A Low-Cost EMFI Platform Compared to BBI and Voltage Fault Injection using TDC & External VCC Measurements.	FDTC	2023	DBLP DOI BibTeX RDF
18	Yutong Zhao, Yuguo Xiang, Fan Ye 0001, Junyan Ren	A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement.	ISCAS	2023	DBLP DOI BibTeX RDF
18	Hua Cheng Lu, Yong Wang, Junqi Chen, Dahuan Zhang, Zhike Li	TDC: Pool-Level Object Cache Replacement Algorithm Based on Temperature Density.	ICA3PP (1)	2023	DBLP DOI BibTeX RDF
18	Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia	A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC.	ASICON	2023	DBLP DOI BibTeX RDF
18	Man-Jae Yang, Goen Hoe Kim, Kang-Yoon Lee	A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter.	ISOCC	2023	DBLP DOI BibTeX RDF
18	Yongseung Lee, Donghun Kim, Jongsun Kim	A GaN Driver IC With a TDC-Based Dead-Time Controller For GaN DC-DC Buck Converters.	ISOCC	2023	DBLP DOI BibTeX RDF
18	Lizhi Xiang, Miao Yin, Chengming Zhang 0006, Aravind Sukumaran-Rajam, P. Sadayappan, Bo Yuan 0001, Dingwen Tao	TDC: Towards Extremely Efficient CNNs on GPUs via Hardware-Aware Tucker Decomposition.	PPoPP	2023	DBLP DOI BibTeX RDF
18	Yoondeok Na, Seokho Yun, Myung-Jae Lee, Youngcheol Chae	An 8.5ps Resolution, $2000\mu\mathrm{m}^{2}$ Phase-Domain Delta-Sigma TDC for Lidar Applications.	A-SSCC	2023	DBLP DOI BibTeX RDF
18	Zeli Li, Tianrui Lyu, Kaiyou Li, Haoxin Zheng, Zhuohang Ye, Shengzhao Su, Jianping Guo, Yang Liu	An 80-dB Dynamic Range Hybrid Pulse-Phase Analog Front-End Circuit Cooperating With a Low-Resolution TDC for LiDAR.	A-SSCC	2023	DBLP DOI BibTeX RDF
18	Hongzhi Liang, Yi Shen 0007, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu	A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.	A-SSCC	2023	DBLP DOI BibTeX RDF
18	Biswajit Mishra, Purvi Patel	Energy Harvester Powered Fully Digital ECG Front End Acquisition with Integrated TDC.	APCCAS	2023	DBLP DOI BibTeX RDF
18	Ziyi Chen 0002, Yi Zhou 0017, Rong-Rong Chen	Multi-Agent Off-Policy TDC with Near-Optimal Sample and Communication Complexities.	Trans. Mach. Learn. Res.	2022	DBLP BibTeX RDF
18	Seonghyeok Park, Bumjun Kim, Su-Hyun Han 0001, Junhee Cho, Jung-Hoon Chun, Jaehyuk Choi 0001, Seong-Jin Kim	An 80 × 60 Flash LiDAR Sensor With In-Pixel Delta-Intensity Quaternary Search Histogramming TDC.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen	A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Fabio Garzetti, Nicola Lusardi, Enrico Ronconi, Andrea Costa, Santiago Tarrago Velez, Christophe Galland, Angelo Geraci	Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements.	IEEE Access	2022	DBLP DOI BibTeX RDF
18	Van Nhan Nguyen, Xuan Thanh Pham, Jong-Wook Lee	An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
18	Azad Ozan Korkan, Heba Yuksel	A Novel Time-to-Amplitude Converter and a Low-Cost Wide Dynamic Range FPGA TDC for LiDAR Application.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
18	Mojtaba Parsakordasiabi, Ion Vornicu, Ángel Rodríguez-Vázquez, Ricardo Carmona-Galán	An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
18	Scott Tancock, John G. Rarity, Naim Dahnoun	The Wave-Union Method on DSP Blocks: Improving FPGA-Based TDC Resolutions by 3x With a 1.5x Area Increase.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
18	Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal	A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
18	Peng Chen 0022, Jun Yin 0001, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski	Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Peng Chen 0022, Xi Meng, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski	A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Wei Zhang, Rui Ma 0007, Xiayu Wang, Hao Zheng, Zhangming Zhu	A High Linearity TDC With a United-Reference Fractional Counter for LiDAR.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Jin Hu 0006, Xiayu Wang, Dong Li, Yang Liu 0106, Rui Ma 0007, Zhangming Zhu	A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Fei Yuan 0005	Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Foad Arvani, Tony Chan Carusone	A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Pedram Naghieh, Ehsan Rahiminejad	An 8-bit Hybrid TDC/Single-Slope ADC with an Improved Continuous-Time Comparator.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
18	Jing Gao 0002, Ningxi Yan, Kaiming Nie, Zhiyuan Gao, Jiangtao Xu	A 2.44μs row conversion time 12-bit high-speed differential single-slope ADC with TDC applied to CMOS image sensor.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
18	Lizhi Xiang, Miao Yin, Chengming Zhang 0006, Aravind Sukumaran-Rajam, P. Sadayappan, Bo Yuan 0001, Dingwen Tao	TDC: Towards Extremely Efficient CNNs on GPUs via Hardware-Aware Tucker Decomposition.	CoRR	2022	DBLP DOI BibTeX RDF
18	Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada	4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
18	Jiyun Tong, Sha Wang, Shuang Zhang, Mengdi Zhang, Ye Zhao, Fazhan Zhao	A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC.	Sensors	2022	DBLP DOI BibTeX RDF
18	Li Xiang	Pulse Shrinking TDC External Captures.		2022	DOI RDF
18	Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher.	DSD	2022	DBLP DOI BibTeX RDF
18	Chaeyoung Jang, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim	A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC.	ICEIC	2022	DBLP DOI BibTeX RDF
18	Rodrigo N. Wuerdig, Bruno Canal, Tiago R. Balen, Sergio Bampi	Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC.	SBCCI	2022	DBLP DOI BibTeX RDF
18	Su-Hyun Han 0001, Bumjun Kim, Seonghyeok Park, Yongjae Park, Jung-Hoon Chun, Jaehyuk Choi 0001, Seong-Jin Kim	A 100×80 CMOS Flash LiDAR Sensor with 0.0011mm2 In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADC.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
18	Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull	A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
18	Haoyi Zhao, Fa Foster Dai	A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment.	ISSCC	2022	DBLP DOI BibTeX RDF
18	Seonghyeok Park, Bumjun Kim, Junhee Cho, Jung-Hoon Chun, Jaehyuk Choi 0001, Seong-Jin Kim	An 80×60 Flash LiDAR Sensor with In-Pixel Histogramming TDC Based on Quaternary Search and Time-Gated Δ-Intensity Phase Detection for 45m Detectable Range and Background Light Cancellation.	ISSCC	2022	DBLP DOI BibTeX RDF
18	Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen	A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology.	ISSCC	2022	DBLP DOI BibTeX RDF
18	Fei Yuan 0005	Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC.	ISCAS	2022	DBLP DOI BibTeX RDF
18	Sergio Moreno, Victor Moro, Ángel Diéguez	A 72-bin in-pixel mixed-signal TDC for SPAD-based fluorescence lifetime measurements.	DCIS	2022	DBLP DOI BibTeX RDF
18	Yutong Zhao, Fan Ye 0001, Junyan Ren	A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC.	APCCAS	2022	DBLP DOI BibTeX RDF