Search results for "transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Michel Renovell, P. Huc, Yves Bertrand	Serial transistor network modeling for bridging fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	serial transistor network modeling, voting model, biased voting model, relative transistor strength, SPICE pre-simulation, fault simulation procedure, CMOS logic, fault diagnosis, logic testing, integrated circuit testing, digital simulation, circuit analysis computing, CMOS logic circuits, SPICE, integrated circuit modelling, bridging fault simulation
77	Jacob White 0001, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong 0001	Advances in transistor timing, simulation, and optimization (tutorial abstract).	ICCAD	1999	DBLP DOI BibTeX RDF
69	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware sleep transistor design for reliable power-gating.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, sizing, sleep-transistor, nbti
69	Zuying Luo	General transistor-level methodology on VLSI low-power design.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	nanometer, transistor level, simulation, optimization
66	Michael A. Riepe, Karem A. Sakallah	Transistor placement for noncomplementary digital VLSI cell synthesis.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Cell Synthesis, Euler graphs, noncomplementary circuits, sequence pair optimization, transistor chaining, transistor placement, digital circuits, benchmark circuits
65	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
63	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
60	Jason Cong, Lei He 0001	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
57	Kaijian Shi, David Howard	Challenges in sleep transistor design and implementation in low-power designs.	DAC	2006	DBLP DOI BibTeX RDF	methodology, low-power design, power gating, sleep transistor
57	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
57	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
53	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells.	ISCAS	2006	DBLP DOI BibTeX RDF
51	Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
51	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
48	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
48	Víctor H. Champac, Antonio Rubio 0001, Joan Figueras	Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
47	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
47	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
47	Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
47	Renato E. B. Poli, Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis	Unified Theory to Build Cell-Level Transistor Networks from BDDs.	SBCCI	2003	DBLP DOI BibTeX RDF
47	Chia-Pin R. Liu, Jacob A. Abraham	Transistor Level Synthesis for Static CMOS Combinational Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
47	Razak Hossain, Menghui Zheng, Alexander Albicki	Reducing power dissipation in CMOS circuits by signal probability based transistor reordering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
47	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
47	Tatjana Serdar, Carl Sechen	AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths.	ICCAD	1999	DBLP DOI BibTeX RDF
45	Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang	A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	DSTN, low power, MTCMOS, sleep transistor
45	Ahmad Sabirin Zoolfakar, Hashimah Hashim	Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	ion implantation, depletion, Enhancement, transistor
45	Ian Kuon, Jonathan Rose	Automated transistor sizing for FPGA architecture exploration.	DAC	2008	DBLP DOI BibTeX RDF	optimization, FPGA, transistor sizing
45	Jie Gu 0003, Hanyong Eom, Chris H. Kim	Sleep transistor sizing and control for resonant supply noise damping.	ISLPED	2007	DBLP DOI BibTeX RDF	resonant supply noise, sleep transistor, damping
45	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
45	Zhiyuan Li, Fengchang Lai, Mingyan Yu	Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	V-NPN transistor, deep n-well CMOS process, high-precision, input bias current cancellation, operational amplifier, low-noise
45	Rupesh S. Shelar, Sachin S. Sapatnekar	An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Low Power, Logic Synthesis, Pass Transistor Logic
45	Paul I. Pénzes, Mika Nyström, Alain J. Martin	Transistor sizing of energy-delay--efficient circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
45	Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky	Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
45	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing
42	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
42	Vishal Khandelwal, Ankur Srivastava 0001	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
42	Vishal Khandelwal, Ankur Srivastava 0001	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
42	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
42	H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan	Carbon nanotube transistor circuits: models and tools for design and performance optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
42	Hayssam El-Razouk, Zine Abid	A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits.	CCECE	2006	DBLP DOI BibTeX RDF
42	Himanshu Thapliyal, A. Prasad Vinod 0001	Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Changbo Long, Lei He 0001	Distributed sleep transistor network for power reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
42	Changbo Long, Lei He 0001	Distributed sleep transistor network for power reduction.	DAC	2003	DBLP DOI BibTeX RDF
42	Krzysztof S. Berezowski	Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis.	DSD	2001	DBLP DOI BibTeX RDF
42	Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek	Minimizing gate capacitances with transistor sizing.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
42	Piotr R. Sidorowicz	Modeling and Testing Transistor Faults in Content-Addressable Memories.	MTDT	1999	DBLP DOI BibTeX RDF
41	Alexander Chatzigeorgiou, Spiridon Nikolaidis 0001	Collapsing the Transistor Chain to an Effective Single Equivalent Transistor.	DATE	1998	DBLP DOI BibTeX RDF
39	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
39	Wojciech Maly	Vertical slit transistor based integrated circuits (VeSTICs) paradigm.	ISPD	2009	DBLP DOI BibTeX RDF	dual gate transistor, ic deign-manufacturing paradigm, vertical channel, vesfet, 3d integration, regular fabric, dfm
39	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Transistor-level layout of high-density regular circuits.	ISPD	2009	DBLP DOI BibTeX RDF	transistor layout, placement and routing, regular fabric, dfm
39	Suman Datta	Low voltage tunnel transistor architecture and its viability for energy efficient logic applications.	ISLPED	2009	DBLP DOI BibTeX RDF	design, tunnel, transistor
39	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	Dual-threshold pass-transistor logic design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual threshold, pass transistor, low power, leakage
39	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
39	Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis	Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.	ISQED	2008	DBLP DOI BibTeX RDF	Transistor networks, logic synthesis, BDDs, Logical effort
39	Guy Dupenloup, Thierry Lemeunier, Roland Mayr	Transistor abstraction for the functional verification of FPGAs.	DAC	2006	DBLP DOI BibTeX RDF	cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification
39	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Exact minimum-width transistor placement without dual constraint for CMOS cells.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	exact minimum-width transistor placement, non-dual, boolean satisfiability
39	Abhijit Das	On the Transistor Sizing Problem.	VLSI Design	2000	DBLP DOI BibTeX RDF	Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint
39	Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama	One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.	ISMVL	1997	DBLP DOI BibTeX RDF	cellular logic image processing, template-matching operations, universal literal, threshold operation, multi-layer interconnectio, parallel template-matching, one-transistor-cell, content-addressable memory, cellular logic
39	S. C. Prasad, Kaushik Roy 0001	Transistor reordering for power minimization under delay constraint.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	critical path enumeration, gate input reordering, transistor reordering, power estimation, circuit optimization
39	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
36	Aswin Sreedhar, Sandip Kundu	Modeling and analysis of non-rectangular transistors caused by lithographic distortions.	ICCD	2008	DBLP DOI BibTeX RDF
36	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
36	Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate	Characterization of subthreshold MOS mismatch in transistors for VLSI systems.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
36	Toru Fujimura, Shigetoshi Nakatake	Transistor-level programmable MOS analog IC with body biasing.	ISCAS	2008	DBLP DOI BibTeX RDF
36	Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki	Transistor-level based defect tolerance for reliable nanoelectronics.	AICCSA	2008	DBLP DOI BibTeX RDF
36	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold Pass Transistor Logic for Ultra-Low Power Operation.	ISVLSI	2007	DBLP DOI BibTeX RDF
36	Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen	A technique for selecting CMOS transistor orders.	ICCD	2007	DBLP DOI BibTeX RDF
36	Dimitri Kagaris, Themistoklis Haniotakis	Transistor-Level Synthesis for Low-Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
36	Feng Shi 0010, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
36	Leomar S. da Rosa Jr., Felipe S. Marques 0001, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Fast disjoint transistor networks from BDDs.	SBCCI	2006	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, switch theory, CMOS gates
36	Emrah Acar, Peter Feldmann	Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA).	ISCAS	2006	DBLP DOI BibTeX RDF
36	D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel	SOI Transistor Model for Fast Transient Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF
36	Spiridon Nikolaidis 0001, Haroula Pournara, Alexander Chatzigeorgiou	Output Waveform Evaluation of Basic Pass Transistor Structure.	PATMOS	2002	DBLP DOI BibTeX RDF
36	Li Ding 0002, Pinaki Mazumder	Optimal Transistor Tapering for High-Speed CMOS Circuits.	DATE	2002	DBLP DOI BibTeX RDF
36	Hai Zhou 0001, Adnan Aziz	Buffer minimization in pass transistor logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
36	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for low power CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
36	Michel R. Dagenais, Serge Gaiotti, Nicholas C. Rumin	Transistor-level estimation of worst-case delays in MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
36	Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu	A fast transistor-chaining algorithm for CMOS cell layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
36	Martin Lefebvre 0001, Chong Chan, Grant Martin	Transistor placement and interconnect algorithms for leaf cell synthesis.	EURO-DAC	1990	DBLP DOI BibTeX RDF
36	Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin	Worst-case Delay Estimation of Transistor Groups.	DAC	1989	DBLP DOI BibTeX RDF
36	Kye S. Hedlund	Aesop: A Tool for Automated Transistor Sizing.	DAC	1987	DBLP DOI BibTeX RDF
35	Hong Zhu 0009, Volkan Kursun	A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells.	ISCAS	2014	DBLP DOI BibTeX RDF
33	Sajad Loan, S. Qureshi, S. Sundar Kumar Iyer	Investigation of a Multizone Drift Doping Based Lateral Bipolar Transistor on Buried Oxide Thick Step.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	Multizone step, multizone doping, lateral bipolar junction transistor, buried oxide thick step, breakdown voltage
33	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
33	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Post-layout leakage power minimization based on distributed sleep transistor insertion.	ISLPED	2004	DBLP DOI BibTeX RDF	sub-threshold current, leakage power, sleep transistor
33	Wen-Yaw Chung, Mao-Hsiang Yeh, Jia-Chyi Chen, Shen-Kan Hsiung, Dorota G. Pijanowska, Wladyslaw Torbicz, Jung-Chuan Chou, Tai-Ping Sun	Design of a Low-voltage Instrumentation Amplifier for Enzyme-Extended-Gate Field Effect Transistor Based Urea Sensor Application.	DELTA	2002	DBLP DOI BibTeX RDF	bulk-driven amplifier, enzyme, extended-gate field effect transistor, urea concentration, instrumentation amplifier
33	Savithri Sundareswaran, R. Venkatesan, S. Bhaskar	An Assertion Based Technique for Transistor Level Dynamic Power Estimation.	VLSI Design	2000	DBLP DOI BibTeX RDF	dynamic power estimation, transistor level, assertions
33	Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki	Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	DFT circuit, test generation, pass-transistor logic, stuck-on fault
33	Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	Logic synthesis for large pass transistor circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	logic synthesis, BDD, Pass transistor logic
33	Arunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay	Multilevel Factorization Technique for Pass Transistor Logic.	VLSI Design	1996	DBLP DOI BibTeX RDF	algebraic factorization, PTL networks, pass transistor logic
30	C. Tabery, M. Craig, Gert Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs	Process Window and Device Variations Evaluation using Array-Based Characterization Circuits.	ISQED	2006	DBLP DOI BibTeX RDF	transistor array, transistor matching, via yield, DOE ROM, novel test circuits, DFM
30	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	ISLPED	2005	DBLP DOI BibTeX RDF	Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt
30	Hassan Ihs, Christian Dufaza	Tolerance DC bands of CMOS operational amplifier.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tolerance DC bands, CMOS operational amplifier, DC node voltages, data tolerance bands, foundry process fluctuations, DC branch current, OA, supply voltage, catastrophic defects, transistor connections, optimization, fault diagnosis, integrated circuit testing, fault detection, fault model, fault simulation, circuit optimisation, operational amplifiers, integrated circuit modelling, transistor size, CMOS analogue integrated circuits, design parameters
30	Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis	Switch level optimization of digital CMOS gate networks.	ISQED	2009	DBLP DOI BibTeX RDF
30	Alexander L. Stempkovsky, Alexey Glebov, Sergey Gavrilov	Calculation of stress probability for NBTI-aware timing analysis.	ISQED	2009	DBLP DOI BibTeX RDF
30	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
30	Tze Wee Chen, Kyunglok Kim, Young Moon Kim, Subhasish Mitra	Gate-Oxide Early Life Failure Prediction.	VTS	2008	DBLP DOI BibTeX RDF
30	Aswin Sreedhar, Sandip Kundu	On modeling impact of sub-wavelength lithography on transistors.	ICCD	2007	DBLP DOI BibTeX RDF
30	Pablo Aguirre, Fernando Silveira	Bias circuit design for low-voltage cascode transistors.	SBCCI	2006	DBLP DOI BibTeX RDF	CMOS, low voltage, analog design
30	Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume	Energy-efficient FPGA interconnect architecture design (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF