Search results for "transistors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57	Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi	Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors.	SBCCI	2008	DBLP DOI BibTeX RDF	TAT, TST, association of transistors, measurements, device modeling
57	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
51	Jin-Kyu Park, Keun-Ho Lee, Chang-Sub Lee, Gi-Young Yang, Young-Kwan Park, Jeong-Taek Kong	Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver.	ISQED	2002	DBLP DOI BibTeX RDF	CURRENT DEGRADATION, ABNORMALLY STRUCTURED MOS, MODELING
51	Shoujue Wang, Xunwei Wu, Hongjuan Feng	The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors.	ISMVL	1995	DBLP DOI BibTeX RDF	high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
45	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
45	Sherif A. Tawfik, Volkan Kursun	Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.	ISQED	2008	DBLP DOI BibTeX RDF
45	Changbo Long, Jinjun Xiong, Lei He 0001	On optimal physical synthesis of sleep transistors.	ISPD	2004	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
44	Takao Waho	Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits.	ISMVL	1995	DBLP DOI BibTeX RDF	resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability
44	G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee	Analysis of temperature dependence of Si-Ge HBT.	VLSI Design	1995	DBLP DOI BibTeX RDF	semiconductor materials, heterojunction bipolar transistors, Ge-Si alloys, heterojunction bipolar transistors, Ge mole-fraction, two dimensional device simulator, BISOF, current gain, graded HBT, 200 to 300 K, simulation, finite element method, finite element analysis, FEM, temperature dependence, SiGe, thermal analysis, semiconductor device models
39	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
39	Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng	A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects.	ICCAD	2008	DBLP DOI BibTeX RDF
38	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.	NanoNet	2009	DBLP DOI BibTeX RDF	low-energy circuits, single electron transistors, binary decision diagram logic circuits
38	Rafail Lashevsky, K. Takaara, M. Souma	The efficiency of neuron-MOS transistors in threshold logic.	Soft Comput.	1999	DBLP DOI BibTeX RDF	Neuron MOS-transistors, threshold gate with alterable parameters, threshold logic
38	Yen-Kuei Chu, Hsiu-Sheng Lin, Po-Chou Lai	Research of a Fast High Voltage Semiconductor Switch.	ISPA	2010	DBLP DOI BibTeX RDF	Pulse Forming Networks (PFNs), Pulse Repetition Frequency (PRF), Metal Oxide Semiconductors Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs)
38	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation.	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
38	Hong Hao, Edward J. McCluskey	Analysis of Gate Oxide Shorts in CMOS Circuits.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	resistance dependence, voltage dependence, pattern dependence, logic gate operation, p-channel transistors, n-channel transistors, CMOS integrated circuits, integrated logic circuits, CMOS circuits, logic gates, defect models, temperature dependence, gate oxide shorts, semiconductor device models
32	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
32	Robert J. Bonneau, George O. Ramseyer, Tom Renz, Claire Thiem	A Mathematical Architecture for Molecular Computing.	AIPR	2007	DBLP DOI BibTeX RDF	molecular computing
32	Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.	Encountering gate oxide breakdown with shadow transistors to increase reliability.	SBCCI	2008	DBLP DOI BibTeX RDF	gate oxide breakdown, modeling, redundancy, logic design, nanotechnology, organic computing, transistor
32	Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga	High-voltage operational amplifier based on dual floating-gate transistors.	ISCAS	2006	DBLP DOI BibTeX RDF
32	Mustapha Chérif-Eddine Yagoub, Jing Xian Li, Farah A. Mohammadi	Méthode Optimale de Modélisation de Transistors Haute Fréquence.	CCECE	2006	DBLP DOI BibTeX RDF
32	David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler	Indirect programming of floating-gate transistors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
32	Paula López 0001, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello	Performance analysis of high-speed MOS transistors with different layout styles.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
32	Alessandro Girardi, Sergio Bampi	LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.	DATE	2003	DBLP DOI BibTeX RDF
32	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi	Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology.	SBCCI	2003	DBLP DOI BibTeX RDF
32	João P. B. Botelho, Leonardo Bruno de Sá, Pedro F. Vieira, Antonio Carneiro de Mesquita Filho	An Experiment on Nonlinear Synthesis Using Evolutionary Techniques Based only on CMOS Transistors.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
32	Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao	Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.	VLSI Design	2003	DBLP DOI BibTeX RDF
32	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
32	Ming-Jiang Zhou, Herbert De Smet, Anita De Bruycker, André Van Calster	A 2-D boundary element method approach to the simulation of DMOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
32	Satoshi Sugahara, Masaaki Tanaka	Spin MOSFETs as a basis for spintronics.	ACM Trans. Storage	2006	DBLP DOI BibTeX RDF	spin MOSFETs, spin transistors, MOSFETs, Spintronics
32	Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand	Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	minimal-length transistors, fault modeling, gate oxide short
32	Jiann-Shiun Yuan	Overview of SiGe Technology Modeling and Application.	ISQED	2000	DBLP DOI BibTeX RDF	SiGe heterojunction bipolar transistors, wireless communications
32	Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal	Transistor Modeling for the VDSM Era.	ISQED	2000	DBLP DOI BibTeX RDF	field effect transistors, parameter extraction, SPICE, device modeling
32	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
32	Vikas Kaushal, Quentin Diduck, Martin Margala	Study of leakage current mechanisms in ballistic deflection transistors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation
32	Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy 0001	Analysis of super cut-off transistors for ultralow power digital logic circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	carbon nanotube FETs, tunneling transistors
26	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
26	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
26	Sherif A. Tawfik, Volkan Kursun	Low power and robust 7T dual-Vt SRAM circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Zhiyu Liu, Volkan Kursun	PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Jaume Abella 0001, Xavier Vera, Antonio González 0001	Penelope: The NBTI-Aware Processor.	MICRO	2007	DBLP DOI BibTeX RDF
26	Bernabé Linares-Barranco, Teresa Serrano-Gotarredona	A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
26	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.	DAC	2006	DBLP DOI BibTeX RDF	subthreshold logic, ultra-low power design, logical effort
26	Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante	Combining low-leakage techniques for FPGA routing design.	FPGA	2005	DBLP DOI BibTeX RDF	low leakage, FPGA, power
26	Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio	A constant-gm rail-to-rail op amp input stage using dynamic current scaling technique.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
26	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
26	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
26	Robert W. Newcomb, Chai-Hung Yang, Angela Hodge-Miller	Quantum dot neural network neurons.	ICARCV	2002	DBLP DOI BibTeX RDF
26	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou	A general subthreshold MOS translinear theorem.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
26	Tak-Kwong Ng, S. Lennart Johnsson	Generation of layouts from MOS circuit schematics: a graph theoretic approach.	DAC	1985	DBLP DOI BibTeX RDF
26	Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang 0003, Faquir C. Jain	Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	threshold voltage and quantum dot transistor, Low power
26	Ratul Kumar Baruah, Santanu Mahapatra	Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors.	VLSI Design	2009	DBLP DOI BibTeX RDF
26	Aswin Sreedhar, Sandip Kundu	Modeling and analysis of non-rectangular transistors caused by lithographic distortions.	ICCD	2008	DBLP DOI BibTeX RDF
26	Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang 0003, Faquir C. Jain	Programmable threshold voltage using quantum dot transistors for low-power mobile computing.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Viktor Gruev, Zheng Yang 0004, Jan Van der Spiegel	Low power linear current mode imager with 1.5 transistors per pixel.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Yukiya Miura, Jiro Kato	Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.	DFT	2008	DBLP DOI BibTeX RDF
26	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
26	Zbysek Gajda, Lukás Sekanina	Reducing the number of transistors in digital circuits using gate-level evolutionary design.	GECCO	2007	DBLP DOI BibTeX RDF	digital circuits, evolvable hardware, evolutionary design
26	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
26	Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel	Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors.	ISCAS	2007	DBLP DOI BibTeX RDF
26	David W. Graham, Paul E. Hasler	Run-Time Programming of Analog Circuits Using Floating-Gate Transistors.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Mahdi Pourfath, Hans Kosina	Fast Convergent Schrödinger-Poisson Solver for the Static and Dynamic Analysis of Carbon Nanotube Field Effect Transistors.	LSSC	2005	DBLP DOI BibTeX RDF
26	Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi 0001, Yasuo Takahashi	A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.	ISMVL	2005	DBLP DOI BibTeX RDF
26	Yiming Li 0005, Kuen-Yu Huang	Numerical Simulation of Self-heating InGaP/GaAs Heterojunction Bipolar Transistors.	International Conference on Computational Science (3)	2005	DBLP DOI BibTeX RDF
26	Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi	A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
26	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
26	Ulf Schlichtmann	Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development.	DSD	2002	DBLP DOI BibTeX RDF
26	Jung Hyun Choi, Sergio Bampi	OTA Amplifiers Design on Digital Sea-of-Transistors Array.	DATE	1999	DBLP DOI BibTeX RDF
26	Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer	An integrated system for assigning signal flow directions to CMOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
26	Yusuf Leblebici, Sung-Mo Kang	Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
26	M. Sytrzycki	Modeling of gate oxide shorts in MOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
26	Geoffrey M. Brown, Miriam Leeser	From Programs to Transistors: Verifying Hardware Synthesis Tools.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
25	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
25	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
25	Yukiya Miura	Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits
25	Sergio Bermejo	Independent Component Analysis for Solid-State Chemical Sensor Arrays.	Appl. Intell.	2006	DBLP DOI BibTeX RDF	chemical sensing, ion-selective field effect transistors, independent component analysis, array processing
25	Paul Beckett	Exploiting multiple functionality for nano-scale reconfigurable systems.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	chalcogenide, double gate transistors, multi-valued RAM, multiple functionality, resonant tunneling, nanotechnology, reconfigurable systems, carbon nanotube, nanoelectronics, RTD
25	Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier	Few electron devices: towards hybrid CMOS-SET integrated circuits.	DAC	2002	DBLP DOI BibTeX RDF	Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics
25	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
25	Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum	Standard CMOS active pixel image sensors for multimedia applications.	ARVLSI	1995	DBLP DOI BibTeX RDF	CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain
25	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
25	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
25	Olivier Betschi, Ken Choi	Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors.	ISOCC	2019	DBLP DOI BibTeX RDF
25	Varvara Bezhenova, Alicja Malgorzata Michalowska-Forsyth	Aspect ratio of radiation-hardened MOS transistors - Modelling of the equivalent channel dimensions of integrated MOS transistors in radiation-hardened enclosed layout.	Elektrotech. Informationstechnik	2018	DBLP DOI BibTeX RDF
25	Manoj Kumar 0005, Sandeep Kumar Arya, Sujata Pandey	Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate	CoRR	2012	DBLP BibTeX RDF
25	Isabelle Ferain, Cynthia A. Colinge, Jean-Pierre Colinge	Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors.	Nat.	2011	DBLP DOI BibTeX RDF
25	Marc Michaillat	Paramètres matériau pour la simulation de transistors bipolaires à hétérojonctions Si/SiGe et Si/SiGeC. (Material parameters for the simulation of SiGe- and SiGeC-based heterojonction bipolar transistors).		2010	RDF
25	Maxime Feraille	Etude du Transport dans les Transistors MOSFETs Contraints: Modélisation Multi-échelle. (Study of Transport Properties in Strained transistors MOSFETs: Multi-scale Approach).		2009	RDF
25	Karim Huet	Modelisation du transport sous contrainte mecanique dans les transistors sub-65 nm pour la Microelectronique CMOS. (Modelling of carrier transport under mechanical strain for sub-65 nm CMOS transistors).		2008	RDF
25	Hao-Chung Kuo	InP/InGaAs Heterojunction Bipolar Transistors and Field-Effect Transistors Grown by Gas -Source Molecular Beam Epitaxy		1999	RDF
19	Joel S. Emer	Accelerating architecture research.	ISPASS	2009	DBLP DOI BibTeX RDF
19	Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy 0001	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.	ISQED	2009	DBLP DOI BibTeX RDF
19	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Soman Purushothaman	A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD.	EIT	2008	DBLP DOI BibTeX RDF
19	Grant Martin	Panel: Best ways to use billions of devices on a chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
19	Hamed F. Dadgour, Vivek De, Kaustav Banerjee	Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim	Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Christian Peters, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli	High-bandwidth floating gate CMOS rectifiers with reduced voltage drop.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Baoyong Chi, Chun Zhang, Zhihua Wang 0001	Bandwidth extension for ultra-wideband CMOS low-noise amplifiers.	ISCAS	2008	DBLP DOI BibTeX RDF