Search results for "variation-tolerant"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Georgios Karakonstantis, Kaushik Roy 0001	Low-Power and Variation-Tolerant Application-Specific System Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
85	Hamid Mahmoodi	Low-Power and Variation-Tolerant Memory Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
85	Meeta Sharma Gupta, Pradip Bose	Variation-Tolerant Microprocessor Architecture at Low Power.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Sachin S. Sapatnekar	Statistical Design of Integrated Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee	Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Swaroop Ghosh	Effect of Variations and Variation Tolerance in Logic Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon	Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Wei Zhang 0012, James Williamson, Li Shang	Power Dissipation.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Aditya Bansal, Rahul M. Rao	Variations: Sources and Characterization.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Nikil Mehta, André DeHon	Low-Power Techniques for FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Bipul C. Paul, Arijit Raychowdhury	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
71	Nikil Mehta, André DeHon	Variation and Aging Tolerance in FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
52	David Wolpert 0001, Paul Ampadu	Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates.	NanoNet	2008	DBLP DOI BibTeX RDF	Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate
39	Jason Cong, Albert Liu, Bin Liu 0006	A variation-tolerant scheduler for better than worst-case behavioral synthesis.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, variation, behavioral synthesis
38	Mohammed Abid Hussain, Madhu Mutyam	Block remap with turnoff: A variation-tolerant cache design technique.	ASP-DAC	2008	DBLP DOI BibTeX RDF
35	Shreyas Sen, Abhijit Chatterjee	Design of process variation tolerant radio frequency low noise amplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
35	Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	current mode singnaling, dynamic overdriving, process variation tolerant
34	Aarti Choudhary, Sandip Kundu	A process variation tolerant self-compensating FinFET based sense amplifier design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sense amplifier, robustness, process -variation, yield, sram, finfet
31	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy 0001	Process Variation Tolerant Online Current Monitor for Robust Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
31	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.	ISQED	2008	DBLP DOI BibTeX RDF
31	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks	Process Variation Tolerant 3T1D-Based Cache Architectures.	MICRO	2007	DBLP DOI BibTeX RDF
29	Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González 0001, Oguz Ergin	Impact of Parameter Variations on Circuits and Microarchitecture.	IEEE Micro	2006	DBLP DOI BibTeX RDF	variation-tolerant design, impact of VLSI on system design, processor architectures, performance and reliability
28	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
28	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.	ISQED	2007	DBLP DOI BibTeX RDF
27	Simone Medardoni, Marcello Lajolo, Davide Bertozzi	Variation tolerant NoC design by means of self-calibrating links.	DATE	2008	DBLP DOI BibTeX RDF
27	Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones	Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
27	David Wolpert 0001, Paul Ampadu	A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip.	DFT	2008	DBLP DOI BibTeX RDF
24	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
23	Spandana Remarsu, Sandip Kundu	On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	self compensating comparator, dithering, thermal sensor
23	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
23	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
23	James W. Tschanz, Keith A. Bowman, Vivek De	Variation-tolerant circuits: circuit solutions and techniques.	DAC	2005	DBLP DOI BibTeX RDF	parameter variation, body bias, high-performance design
22	Jin-O. Seo, Mingoo Seok, SeongHwan Cho	A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
22	Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy	High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
22	Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik	Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
21	Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar	Circuit techniques for dynamic variation tolerance.	DAC	2009	DBLP DOI BibTeX RDF	dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
21	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
16	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy 0001	Coping with Variations through System-Level Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han	A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
15	Shohei Imai, Hideyuki Sato, Kenji Mukai, Hiroshi Okabe	32.3 A Load-Variation-Tolerant Doherty Power Amplifier with Dual-Adaptive-Bias Scheme for 5G Handsets.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang 0002, Yuan Wang 0001, Runsheng Wang, Ru Huang	30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Mao Li, Zhaoqing Wang, Sanu K. Mathew, Vivek De, Mingoo Seok	16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak	9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Jieun Park, Yong Ki Lee, Bohdan Karpinskyy, Yunhyeok Choi, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin	16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm.	ISSCC	2024	DBLP DOI BibTeX RDF
15	Ayush Dahiya, Poornima Mittal, Rajesh Rohilla	Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
15	Xuliang Wang, Xiaosen Liu, Wing-Hung Ki	A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
15	Kangning Wang, Huidong Zhao, Jiliang Liu, Jialu Yin, Zhi Li, Shushan Qiao	A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
15	Jongmin Lee, Minsun Kim, Minhyeok Jeong, Gicheol Shin, Yoonmyung Lee	A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
15	Mithilesh Kumar 0008, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.	Integr.	2022	DBLP DOI BibTeX RDF
15	Bhawna Rawat, Poornima Mittal	A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
15	Soyoun Jeong, Jaerok Kim, Minhyeok Jeong, Yoonmyung Lee	Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
15	Vipul Bhatnagar, Manoj Kumar Pandey, Sujata Pandey	A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
15	Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine	Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS.	ASP-DAC	2022	DBLP DOI BibTeX RDF
15	Jin-O. Seo, Mingoo Seok, SeongHwan Cho	ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory.	ISSCC	2022	DBLP DOI BibTeX RDF
15	Md Mahadi Masnad, Guowu Zhang, Dan-Xia Xu, Yuri Grinberg, Odile Liboiron-Ladouceur	Dimensional Variation Tolerant Inverse Designed Broadband Mode Converter.	OFC	2022	DBLP BibTeX RDF
15	Samuel J. Engers, Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001	MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
15	Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim	Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
15	Neha Sharma, Rajeevan Chandel	Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS.	Int. J. Model. Simul. Sci. Comput.	2021	DBLP DOI BibTeX RDF
15	Dongyeon Kang, Jun Tae Jang, Shinyoung Park, Md. Hasan Raza Ansari, Jong-Ho Bae, Sung-Jin Choi, Dong Myong Kim, Changwook Kim, Seongjae Cho, Dae Hwan Kim	Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System.	IEEE Access	2021	DBLP DOI BibTeX RDF
15	Hasita Veluri, Yida Li, Jessie Xuhua Niu, Evgeny Zamburg, Aaron Voon-Yew Thean	High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks.	IEEE Internet Things J.	2021	DBLP DOI BibTeX RDF
15	Monica Gupta, Kirti Gupta, Neeta Pandey	A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
15	Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee 0002	Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks.	Adv. Intell. Syst.	2021	DBLP DOI BibTeX RDF
15	Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min-Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee 0002	Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks.	Adv. Intell. Syst.	2021	DBLP DOI BibTeX RDF
15	Byungkyu Song, Sehee Lim, Seung-Hyuk Kang, Seong-Ook Jung	Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique.	IEEE Trans. Inf. Forensics Secur.	2021	DBLP DOI BibTeX RDF
15	Kangqiang Pan, Amr M. S. Tosson, Norman Y. Zhou, Lan Wei	A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit.	NANOARCH	2021	DBLP DOI BibTeX RDF
15	Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok	A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device.	ISSCC	2021	DBLP DOI BibTeX RDF
15	Arijit Raychowdhury, Mijung Noh, Keith A. Bowman	Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee.	ISSCC	2021	DBLP DOI BibTeX RDF
15	Jongmin Lee, Yoonmyung Lee	A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security.	A-SSCC	2021	DBLP DOI BibTeX RDF
15	Wen-Jie Lin, Jeng-Han Tsai, Jen-Hao Cheng, Wei-Heng Lin, Tung-Tsen Chiang, Tian-Wei Huang	A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design.	IEEE Access	2020	DBLP DOI BibTeX RDF
15	Gwang Hui Choi, Taehui Na	Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region.	IEEE Access	2020	DBLP DOI BibTeX RDF
15	Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey	A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
15	Song Jin, Songwei Pei, Yu Wang	A variation tolerant scheme for memristor crossbar based neural network designs via two-phase weight mapping and memristor programming.	Future Gener. Comput. Syst.	2020	DBLP DOI BibTeX RDF
15	Jooyoon Kim, Jongsun Park 0001	Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit.	ISOCC	2020	DBLP DOI BibTeX RDF
15	Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung	Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
15	Yongmin Lee, Yoonmyung Lee	A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
15	Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto	An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.	ICECS	2019	DBLP DOI BibTeX RDF
15	Jinseok Kim 0004, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim	Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
15	Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling	A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
15	Furkan Peker, Mustafa Altun	A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
15	Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag	A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
15	Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang 0006	A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.	IEEE Access	2018	DBLP DOI BibTeX RDF
15	Jaeyoung Park, Young Uk Yim	Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
15	Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula	Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
15	Shinichi Nishizawa, Hidetoshi Onodera	Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
15	Yi Xu, Jun Yang 0002, Rami G. Melhem	A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network.	ACM J. Emerg. Technol. Comput. Syst.	2018	DBLP DOI BibTeX RDF
15	Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung	Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
15	Shourya Gupta, Kirti Gupta, Neeta Pandey	Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
15	Woo-Rham Bae, Kyung Jean Yoon, Taeksang Song, Borivoje Nikolic	A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
15	Yi Yu, Jia Yuan, Lin-Lin Xie, Shushan Qiao, Yong Hei	A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
15	Asghar Bahramali, Marisa López-Vallejo	A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications.	PATMOS	2018	DBLP DOI BibTeX RDF
15	Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung	CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA.	ICSCA	2018	DBLP DOI BibTeX RDF
15	Khawar Sarfraz, Jin He 0003, Mansun Chan	A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
15	Sheng Wang 0005, Chen Chen 0058, Xiaoyan Xiang, Jian-Yi Meng	A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
15	Abdullah El-Bayoumi, Hassan Mostafa, Ahmed M. Soliman	A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
15	Yi Wang 0003, Lisha Dong, Rui Mao 0001	P-Alloc: Process-Variation Tolerant Reliability Management for 3D Charge-Trapping Flash Memory.	ACM Trans. Embed. Comput. Syst.	2017	DBLP DOI BibTeX RDF
15	Kangwook Jo, Hongil Yoon	Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
15	Sheng Wang 0005, Chen Chen 0058, Xiaoyan Xiang, Jianyi Meng	A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
15	Yimai Peng, Haobo Zhao, Xun Sun, Chen Sun	A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator.	ISVLSI	2017	DBLP DOI BibTeX RDF