Search results for "vesfet"

Found 10 publication records. Showing 10 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Wojciech Maly	Vertical slit transistor based integrated circuits (VeSTICs) paradigm.	ISPD	2009	DBLP DOI BibTeX RDF	dual gate transistor, ic deign-manufacturing paradigm, vertical channel, vesfet, 3d integration, regular fabric, dfm
34	Mikolaj Palgan, Andrzej Pfitzner	Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology.	MIXDES	2018	DBLP DOI BibTeX RDF
34	Andrzej Pfitzner, Beata Kowalska	Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET).	MIXDES	2016	DBLP DOI BibTeX RDF
34	Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly	Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
34	Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly	Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
34	Andrzej Pfitzner	Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET).	MIXDES	2014	DBLP DOI BibTeX RDF
34	Dominik Kasprowicz, Bartosz Swacha	VeSFET as an analog-circuit component.	DDECS	2013	DBLP DOI BibTeX RDF
34	Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly	Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure.	ISPD	2013	DBLP DOI BibTeX RDF
34	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
34	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Performance study of VeSFET-based, high-density regular circuits.	ISPD	2010	DBLP DOI BibTeX RDF	advanced technology., transistor layout, DFM, regular fabric

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