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Publication years (Num. hits)
1969-1989 (16) 1990-1992 (16) 1993-1997 (17) 1998-2001 (18) 2002-2003 (16) 2004-2005 (31) 2006 (36) 2007 (27) 2008 (34) 2009 (33) 2010-2011 (25) 2012-2013 (32) 2014 (20) 2015 (18) 2016-2017 (28) 2018-2019 (24) 2020-2021 (19) 2022-2023 (21)
Publication types (Num. hits)
article(167) incollection(1) inproceedings(256) phdthesis(7)
Venues (Conferences, Journals, ...)
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The graphs summarize 168 occurrences of 125 keywords

Results
Found 435 publication records. Showing 431 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
102Brent Goplen, Sachin S. Sapatnekar Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
82Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee Post-routing redundant via insertion with wire spreading capability. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
67Hao Yu 0001, Joanna Ho, Lei He 0001 Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Thermal and power integrity, parametric 3D-IC design, macromodeling
67Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
67Sy-Yen Kuo YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
63Vasilis F. Pavlidis, Giovanni De Micheli Power distribution paths in 3-D ICS. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF power distribution network, 3-D ICS, 3-D integration, through silicon vias
59Shuai Li, Jin Shi, Yici Cai, Xianlong Hong Vertical via design techniques for multi-layered P/G networks. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
59Kuang-Yao Lee, Ting-Chi Wang Post-routing redundant via insertion for yield/reliability improvement. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
59K. C. Chang 0001, David Hung-Chang Du A preprocessor for the via minimization problem. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF layout routing, via minimization
55Ioannis Savidis, Eby G. Friedman Electrical modeling and characterization of 3-D vias. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Stanley E. Lass Automated printed circuit routing with a stepping aperture. Search on Bibsonomy Commun. ACM The full citation details ... 1969 DBLP  DOI  BibTeX  RDF circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture
47Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng Bus via reduction based on floorplan revising. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF floorplan revising, via reduction, bus routing
47Renato Fernandes Hentschke, Ricardo Reis 0001 A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Kevin W. McCullen Redundant Via Insertion in Restricted Topology Layouts. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002 Yield Improvement by Local Wiring Redundancy. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Brent Goplen, Sachin S. Sapatnekar Thermal via placement in 3D ICs. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF 3-D VLSI, thermal gradient, thermal optimization, thermal via, routing, placement, temperature, finite element analysis, 3-D IC
47Khe-Sing The, Martin D. F. Wong, Jason Cong A layout modification approach to via minimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
47Yang Cai 0003, D. F. Wong 0001 Optimal via-shifting in channel compaction. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
47Khe-Sing The, D. F. Wong 0001, Jason Cong VIA Minimization by Layout Modification. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
43Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001 3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Eric Wong 0002, Sung Kyu Lim 3D floorplanning with thermal vias. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Shweta Chary, Michael L. Bushnell Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong Analysis for Complex Power Distribution Networks Considering Densely Populated Vias. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Manuel Ramírez-Sánchez, Isabel Prieto, Ana Belén Segarra, Inmaculada Banegas, Magdalena Martínez-Cañamero, Germán Domínguez-Vías, Raquel Durán, Francisco Vives, Francisco Alba Asymmetric Pattern of Correlations of Leucine Aminopeptidase Activity between Left or Right Frontal Cortex versus Diverse Left or Right Regions of Rat Brains. Search on Bibsonomy Symmetry The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
40Hugo Castro Noblejas, Jesús Vías Martínez, Matías Francisco Mérida Rodríguez Relation between the Views and the Real Estate Application to a Mediterranean Coastal Area. Search on Bibsonomy ISPRS Int. J. Geo Inf. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
40Manuel Ramírez-Sánchez, Isabel Prieto, Ana Belén Segarra, Inmaculada Banegas, Magdalena Martínez-Cañamero, Germán Domínguez-Vías, Marc de Gasparo Brain Asymmetry: Towards an Asymmetrical Neurovisceral Integration. Search on Bibsonomy Symmetry The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
40Jesús M. Vías, José Rolland, María Luisa Gómez, Carmen Ocaña, Ana Luque Recommendation system to determine suitable and viable hiking routes: a prototype application in Sierra de las Nieves Nature Reserve (southern Spain). Search on Bibsonomy J. Geogr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
40Antonio Rodriguez Cervilla, Siham Tabik, Jesús M. Vías, Matías Mérida, Luis F. Romero Total 3D-viewshed Map: Quantifying the Visible Volume in Digital Elevation Models. Search on Bibsonomy Trans. GIS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
40Luis F. Romero, Siham Tabik, Jesús M. Vías, Emilio L. Zapata Fast clear-sky solar irradiation computation for very large digital elevation models. Search on Bibsonomy Comput. Phys. Commun. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
40Siham Tabik, Jesús M. Vías, Emilio L. Zapata, Luis F. Romero Fast Insolation Computation in Large Territories. Search on Bibsonomy International Conference on Computational Science (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Insolation, horizon computation, very large territories, Globus
40Antonio J. Durán Guardeño, Enrique Daneri-Vias Ratio Asymptotics for Orthogonal Matrix Polynomials with Unbounded Recurrence Coefficients. Search on Bibsonomy J. Approx. Theory The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40M. Balmont, Isabelle Bord-Majek, B. Poupard, Laurent Béchou, Yves Ousten Highlighting two integration technologies based on vias: Through silicon vias and embedded components into PCB. Strengths and weaknesses for manufacturing and reliability. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
40Dehia Ait-Ferhat Design of exact solutions for the manufacturing of "vias" using DSA technology. (Conception de solutions exactes pour la fabrication de "vias" en utilisant la technologie DSA). Search on Bibsonomy 2018   RDF
35Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Lili Zhou, Cherry Wakayama, C.-J. Richard Shi CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Hailong Yao, Yici Cai, Xianlong Hong CMP-aware Maze Routing Algorithm for Yield Enhancement. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar Temperature-aware routing in 3D ICs. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001 Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. Search on Bibsonomy SBCCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3d circuits, cell shifting, placement, quadratic placement
35Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng Integrating dynamic thermal via planning with 3D floorplanning algorithm. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3D floorplanning, thermal optimization, thermal via
35Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao Post-routing redundant via insertion and line end extension with via density consideration. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SQP optimization, structured and parameterized macromodel, thermal management and simulation
35Takumi Uezono, Kenichi Okada, Kazuya Masu Via Distribution Model for Yield Estimation. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Yukiko Kubo, Atsushi Takahashi 0001 A global routing method for 2-layer ball grid array packages. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF 2-layer routing, ball grid array, cost graph, heuristic, global routing, monotonic, greedy
35Kiyoshi Nikawa How long can we succeed using the OBIRCH and its derivatives? Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Kei-Yong Khoo, Jason Cong An efficient multilayer MCM router based on four-via routing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
35Yang Cai 0003, Martin D. F. Wong Efficient via shifting algorithms in channel compaction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
35Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu Unconstrained via minimization for topological multilayer routing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
32DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De Analytical Model for the Propagation Delay of Through Silicon Vias. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 3D integrated circuits, propagation delay model, dimensional analysis, TSV
32Jingyu Xu, Subarna Sinha, Charles C. Chiang Accurate detection for process-hotspots with vias and incomplete specification. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan Efficient Simulation of Power/Ground Networks with Package and Vias. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32J. Fernando Naveda, K. C. Chang 0001, David Hung-Chang Du A new approach to multi-layer PCB routing with short vias. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
28Norio Kuji, Takako Ishihara EB-Testing-Pad Method and Its Evaluation by Actual Devices. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability
28Ruth Kuchem, Dorothea Wagner, Frank Wagner 0001 Area-Optimal Three-Layer Channel Routing Search on Bibsonomy FOCS The full citation details ... 1989 DBLP  DOI  BibTeX  RDF area optimal routing algorithm, three-layer channel routing, knock-knee mode, three conducting layers, three-layer wirable layout, time complexity, vias, layer assignment, layout algorithms
28Inder S. Gopal, Don Coppersmith, C. K. Wong Optimal Wiring of Movable Terminals. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF wiring channels, movable terminals, VLSI chip design, dynamic programming, optimal algorithms, Analysis of algorithms, NP-complete problems, wiring, vias
23Jason Cong, Guojie Luo An analytical placer for mixed-size 3D placement. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF placement, 3D integration, analytical method
23David S. Kung 0001, Ruchir Puri CAD challenges for 3D ICs. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Yue Xu, Yanheng Zhang, Chris Chu FastRoute 4.0: global router with efficient via minimization. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang Redundant via insertion with wire bending. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF redundant via, wire bending, integer linear program
23Aida Todri, Malgorzata Marek-Sadowska Electromigration study of power-gated grids. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF electromigration, power network
23Pratik J. Shah, Jiang Hu Impact of lithography-friendly circuit layout. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cd variation, lithography, wirelength, routing congestion
23Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han Full-Chip Routing Considering Double-Via Insertion. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Sudhakar M. Reddy, Irith Pomeranz, Chen Liu On tests to detect via opens in digital CMOS circuits. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF constrained stuck-at tests, test generation, DFT, open defects
23Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris A software-supported methodology for designing high-performance 3D FPGA architectures. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin Double-via-driven standard cell library design. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Mohit Pathak, Sung Kyu Lim Thermal-aware Steiner routing for 3D stacked ICs. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Eric Wong 0002, Sung Kyu Lim Whitespace redistribution for thermal via insertion in 3D stacked ICs. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Brent Goplen, Sachin S. Sapatnekar Placement of 3D ICs with Thermal and Interlayer Via Considerations. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Yukiko Kubo, Atsushi Takahashi 0001 Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
23Hao Yu 0001, Joanna Ho, Lei He 0001 Simultaneous power and thermal integrity driven via stapling in 3D ICs. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF structured and parameterized model order reduction, thermal modeling and management
23Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF trade off, design flow, temperature dependency, 3DIC
23Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han Novel full-chip gridless routing considering double-via insertion. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF redundant via insertion, routing, manufacturability
23Kiran Puttaswamy, Gabriel H. Loh Implementing Caches in a 3D Technology for High Performance Processors. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Takayuki Watanabe, Hideki Asai Modeling of power distribution networks with signal lines for SPICE simulators. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Joungho Kim, Junso Pak, Jongbae Park, Hyungsoo Kim Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Yang Yang 0040, Tong Jing, Xianlong Hong, Yu Hu 0002, Qi Zhu 0002, Xiaodong Hu 0001, Guiying Yan Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou 0001 Improved multilevel routing with redundant via placement for yield and reliability. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF redundant via, routing, VLSI, DFM, yield enhancement
23Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Pallav Gupta, Lin Zhong 0001, Niraj K. Jha A High-level Interconnect Power Model for Design Space Exploration. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
23Mehmet Can Yildiz, Patrick H. Madden Preferred direction Steiner trees. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
23Chin-Chih Chang, Jason Cong Pseudopin assignment with crosstalk noise control. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Neil Harrison A Simple via Duplication Tool for Yield Enhancement. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Chin-Chih Chang, Jason Cong An efficient approach to multilayer layer assignment with anapplication to via minimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Sandip Das 0001, Subhas C. Nandy, Bhargab B. Bhattacharya High Performance MCM Routing: A New Approach. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Jun Dong Cho, Majid Sarrafzadeh Four-bend top-down global routing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Chin-Chih Chang, Jason Cong An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
23Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
23Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima Via Minimization for Gridless Layouts. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
20Zhen Fang, Jihua Zhang, Libin Gao, Hongwei Chen, Wenlei Li, Tianpeng Liang, Xudong Cai, Xingzhou Cai, Weicong Jia, Huan Guo, Yong Li Ka-band broadband filtering packaging antenna based on through-glass vias (TGVs). Search on Bibsonomy Frontiers Inf. Technol. Electron. Eng. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20M. Ananda Reddy, R. Pandeeswari, Seok-Bum Ko Non-Bianisotropic Complementary Split Ring Resonator Metamaterial Bandstop Filter Using Cylindrical Metal Vias. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Jogesh Chandra Dash, Debdeep Sarkar A Co-Linearly Polarized Shared Radiator-Based Full-Duplex Antenna With High Tx-Rx Isolation Using vias and Stub Resonator. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Nuo Liu, Xiaoxian Liu, Chenhui Fan Filtering SIW phase shifter based on through quartz vias technology. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Ajay Kumar, Rohit Dhiman Frequency response and transient analysis of through glass packaging vias using matrix-rational approximation (MRA) technique for three-dimensional ICs. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Andreas Bauer, Benjamin H. Zacher, Sven Urschel, Christian Schumann Multilayered PCB-Based Axial Flux Motor Windings with Thermal VIAs to Enhance Thermal Utilization. Search on Bibsonomy IECON The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Eric Beyne, Anne Jourdain, Gerald Beyer Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
20Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
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