Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
102 | Brent Goplen, Sachin S. Sapatnekar |
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
82 | Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee |
Post-routing redundant via insertion with wire spreading capability. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
67 | Hao Yu 0001, Joanna Ho, Lei He 0001 |
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Thermal and power integrity, parametric 3D-IC design, macromodeling |
67 | Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis |
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Sy-Yen Kuo |
YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
63 | Vasilis F. Pavlidis, Giovanni De Micheli |
Power distribution paths in 3-D ICS. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
power distribution network, 3-D ICS, 3-D integration, through silicon vias |
59 | Shuai Li, Jin Shi, Yici Cai, Xianlong Hong |
Vertical via design techniques for multi-layered P/G networks. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
59 | Kuang-Yao Lee, Ting-Chi Wang |
Post-routing redundant via insertion for yield/reliability improvement. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
59 | K. C. Chang 0001, David Hung-Chang Du |
A preprocessor for the via minimization problem. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
layout routing, via minimization |
55 | Ioannis Savidis, Eby G. Friedman |
Electrical modeling and characterization of 3-D vias. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Stanley E. Lass |
Automated printed circuit routing with a stepping aperture. |
Commun. ACM |
1969 |
DBLP DOI BibTeX RDF |
circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture |
47 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
Bus via reduction based on floorplan revising. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
floorplan revising, via reduction, bus routing |
47 | Renato Fernandes Hentschke, Ricardo Reis 0001 |
A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Kevin W. McCullen |
Redundant Via Insertion in Restricted Topology Layouts. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002 |
Yield Improvement by Local Wiring Redundancy. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Brent Goplen, Sachin S. Sapatnekar |
Thermal via placement in 3D ICs. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
3-D VLSI, thermal gradient, thermal optimization, thermal via, routing, placement, temperature, finite element analysis, 3-D IC |
47 | Khe-Sing The, Martin D. F. Wong, Jason Cong |
A layout modification approach to via minimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
47 | Yang Cai 0003, D. F. Wong 0001 |
Optimal via-shifting in channel compaction. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
47 | Khe-Sing The, D. F. Wong 0001, Jason Cong |
VIA Minimization by Layout Modification. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
43 | Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001 |
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Eric Wong 0002, Sung Kyu Lim |
3D floorplanning with thermal vias. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Shweta Chary, Michael L. Bushnell |
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong |
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Manuel Ramírez-Sánchez, Isabel Prieto, Ana Belén Segarra, Inmaculada Banegas, Magdalena Martínez-Cañamero, Germán Domínguez-Vías, Raquel Durán, Francisco Vives, Francisco Alba |
Asymmetric Pattern of Correlations of Leucine Aminopeptidase Activity between Left or Right Frontal Cortex versus Diverse Left or Right Regions of Rat Brains. |
Symmetry |
2023 |
DBLP DOI BibTeX RDF |
|
40 | Hugo Castro Noblejas, Jesús Vías Martínez, Matías Francisco Mérida Rodríguez |
Relation between the Views and the Real Estate Application to a Mediterranean Coastal Area. |
ISPRS Int. J. Geo Inf. |
2022 |
DBLP DOI BibTeX RDF |
|
40 | Manuel Ramírez-Sánchez, Isabel Prieto, Ana Belén Segarra, Inmaculada Banegas, Magdalena Martínez-Cañamero, Germán Domínguez-Vías, Marc de Gasparo |
Brain Asymmetry: Towards an Asymmetrical Neurovisceral Integration. |
Symmetry |
2021 |
DBLP DOI BibTeX RDF |
|
40 | Jesús M. Vías, José Rolland, María Luisa Gómez, Carmen Ocaña, Ana Luque |
Recommendation system to determine suitable and viable hiking routes: a prototype application in Sierra de las Nieves Nature Reserve (southern Spain). |
J. Geogr. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
40 | Antonio Rodriguez Cervilla, Siham Tabik, Jesús M. Vías, Matías Mérida, Luis F. Romero |
Total 3D-viewshed Map: Quantifying the Visible Volume in Digital Elevation Models. |
Trans. GIS |
2017 |
DBLP DOI BibTeX RDF |
|
40 | Luis F. Romero, Siham Tabik, Jesús M. Vías, Emilio L. Zapata |
Fast clear-sky solar irradiation computation for very large digital elevation models. |
Comput. Phys. Commun. |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Siham Tabik, Jesús M. Vías, Emilio L. Zapata, Luis F. Romero |
Fast Insolation Computation in Large Territories. |
International Conference on Computational Science (1) |
2007 |
DBLP DOI BibTeX RDF |
Insolation, horizon computation, very large territories, Globus |
40 | Antonio J. Durán Guardeño, Enrique Daneri-Vias |
Ratio Asymptotics for Orthogonal Matrix Polynomials with Unbounded Recurrence Coefficients. |
J. Approx. Theory |
2001 |
DBLP DOI BibTeX RDF |
|
40 | M. Balmont, Isabelle Bord-Majek, B. Poupard, Laurent Béchou, Yves Ousten |
Highlighting two integration technologies based on vias: Through silicon vias and embedded components into PCB. Strengths and weaknesses for manufacturing and reliability. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
40 | Dehia Ait-Ferhat |
Design of exact solutions for the manufacturing of "vias" using DSA technology. (Conception de solutions exactes pour la fabrication de "vias" en utilisant la technologie DSA). |
|
2018 |
RDF |
|
35 | Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman |
Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong |
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Lili Zhou, Cherry Wakayama, C.-J. Richard Shi |
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Hailong Yao, Yici Cai, Xianlong Hong |
CMP-aware Maze Routing Algorithm for Yield Enhancement. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar |
Temperature-aware routing in 3D ICs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001 |
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
3d circuits, cell shifting, placement, quadratic placement |
35 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Integrating dynamic thermal via planning with 3D floorplanning algorithm. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, thermal optimization, thermal via |
35 | Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao |
Post-routing redundant via insertion and line end extension with via density consideration. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik |
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
SQP optimization, structured and parameterized macromodel, thermal management and simulation |
35 | Takumi Uezono, Kenichi Okada, Kazuya Masu |
Via Distribution Model for Yield Estimation. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Yukiko Kubo, Atsushi Takahashi 0001 |
A global routing method for 2-layer ball grid array packages. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
2-layer routing, ball grid array, cost graph, heuristic, global routing, monotonic, greedy |
35 | Kiyoshi Nikawa |
How long can we succeed using the OBIRCH and its derivatives? |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Kei-Yong Khoo, Jason Cong |
An efficient multilayer MCM router based on four-via routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
35 | Yang Cai 0003, Martin D. F. Wong |
Efficient via shifting algorithms in channel compaction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
35 | Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu |
Unconstrained via minimization for topological multilayer routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
32 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De |
Analytical Model for the Propagation Delay of Through Silicon Vias. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
3D integrated circuits, propagation delay model, dimensional analysis, TSV |
32 | Jingyu Xu, Subarna Sinha, Charles C. Chiang |
Accurate detection for process-hotspots with vias and incomplete specification. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
Efficient Simulation of Power/Ground Networks with Package and Vias. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
32 | J. Fernando Naveda, K. C. Chang 0001, David Hung-Chang Du |
A new approach to multi-layer PCB routing with short vias. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
|
28 | Norio Kuji, Takako Ishihara |
EB-Testing-Pad Method and Its Evaluation by Actual Devices. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability |
28 | Ruth Kuchem, Dorothea Wagner, Frank Wagner 0001 |
Area-Optimal Three-Layer Channel Routing |
FOCS |
1989 |
DBLP DOI BibTeX RDF |
area optimal routing algorithm, three-layer channel routing, knock-knee mode, three conducting layers, three-layer wirable layout, time complexity, vias, layer assignment, layout algorithms |
28 | Inder S. Gopal, Don Coppersmith, C. K. Wong |
Optimal Wiring of Movable Terminals. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
wiring channels, movable terminals, VLSI chip design, dynamic programming, optimal algorithms, Analysis of algorithms, NP-complete problems, wiring, vias |
23 | Jason Cong, Guojie Luo |
An analytical placer for mixed-size 3D placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
placement, 3D integration, analytical method |
23 | David S. Kung 0001, Ruchir Puri |
CAD challenges for 3D ICs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Yue Xu, Yanheng Zhang, Chris Chu |
FastRoute 4.0: global router with efficient via minimization. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang |
Redundant via insertion with wire bending. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
redundant via, wire bending, integer linear program |
23 | Aida Todri, Malgorzata Marek-Sadowska |
Electromigration study of power-gated grids. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
electromigration, power network |
23 | Pratik J. Shah, Jiang Hu |
Impact of lithography-friendly circuit layout. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
cd variation, lithography, wirelength, routing congestion |
23 | Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik |
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han |
Full-Chip Routing Considering Double-Via Insertion. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh |
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Sudhakar M. Reddy, Irith Pomeranz, Chen Liu |
On tests to detect via opens in digital CMOS circuits. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
constrained stuck-at tests, test generation, DFT, open defects |
23 | Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris |
A software-supported methodology for designing high-performance 3D FPGA architectures. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin |
Double-via-driven standard cell library design. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris |
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Mohit Pathak, Sung Kyu Lim |
Thermal-aware Steiner routing for 3D stacked ICs. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Eric Wong 0002, Sung Kyu Lim |
Whitespace redistribution for thermal via insertion in 3D stacked ICs. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Brent Goplen, Sachin S. Sapatnekar |
Placement of 3D ICs with Thermal and Interlayer Via Considerations. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Yukiko Kubo, Atsushi Takahashi 0001 |
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Hao Yu 0001, Joanna Ho, Lei He 0001 |
Simultaneous power and thermal integrity driven via stapling in 3D ICs. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
structured and parameterized model order reduction, thermal modeling and management |
23 | Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis |
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
trade off, design flow, temperature dependency, 3DIC |
23 | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han |
Novel full-chip gridless routing considering double-via insertion. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
redundant via insertion, routing, manufacturability |
23 | Kiran Puttaswamy, Gabriel H. Loh |
Implementing Caches in a 3D Technology for High Performance Processors. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Takayuki Watanabe, Hideki Asai |
Modeling of power distribution networks with signal lines for SPICE simulators. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Joungho Kim, Junso Pak, Jongbae Park, Hyungsoo Kim |
Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Yang Yang 0040, Tong Jing, Xianlong Hong, Yu Hu 0002, Qi Zhu 0002, Xiaodong Hu 0001, Guiying Yan |
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou 0001 |
Improved multilevel routing with redundant via placement for yield and reliability. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
redundant via, routing, VLSI, DFM, yield enhancement |
23 | Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali |
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Pallav Gupta, Lin Zhong 0001, Niraj K. Jha |
A High-level Interconnect Power Model for Design Space Exploration. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Mehmet Can Yildiz, Patrick H. Madden |
Preferred direction Steiner trees. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Chin-Chih Chang, Jason Cong |
Pseudopin assignment with crosstalk noise control. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Neil Harrison |
A Simple via Duplication Tool for Yield Enhancement. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Chin-Chih Chang, Jason Cong |
An efficient approach to multilayer layer assignment with anapplication to via minimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Sandip Das 0001, Subhas C. Nandy, Bhargab B. Bhattacharya |
High Performance MCM Routing: A New Approach. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Jun Dong Cho, Majid Sarrafzadeh |
Four-bend top-down global routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Chin-Chih Chang, Jason Cong |
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani |
Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima |
Via Minimization for Gridless Layouts. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
20 | Zhen Fang, Jihua Zhang, Libin Gao, Hongwei Chen, Wenlei Li, Tianpeng Liang, Xudong Cai, Xingzhou Cai, Weicong Jia, Huan Guo, Yong Li |
Ka-band broadband filtering packaging antenna based on through-glass vias (TGVs). |
Frontiers Inf. Technol. Electron. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
20 | M. Ananda Reddy, R. Pandeeswari, Seok-Bum Ko |
Non-Bianisotropic Complementary Split Ring Resonator Metamaterial Bandstop Filter Using Cylindrical Metal Vias. |
IEEE Trans. Circuits Syst. II Express Briefs |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Jogesh Chandra Dash, Debdeep Sarkar |
A Co-Linearly Polarized Shared Radiator-Based Full-Duplex Antenna With High Tx-Rx Isolation Using vias and Stub Resonator. |
IEEE Trans. Circuits Syst. II Express Briefs |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Nuo Liu, Xiaoxian Liu, Chenhui Fan |
Filtering SIW phase shifter based on through quartz vias technology. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Ajay Kumar, Rohit Dhiman |
Frequency response and transient analysis of through glass packaging vias using matrix-rational approximation (MRA) technique for three-dimensional ICs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Andreas Bauer, Benjamin H. Zacher, Sven Urschel, Christian Schumann |
Multilayered PCB-Based Axial Flux Motor Windings with Thermal VIAs to Enhance Thermal Utilization. |
IECON |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Eric Beyne, Anne Jourdain, Gerald Beyer |
Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran |
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2022 |
DBLP DOI BibTeX RDF |
|