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Publication years (Num. hits)
1990-2000 (31) 2001 (34) 2002 (59) 2003 (80) 2004 (82) 2005 (74) 2006 (133) 2007 (128) 2008 (130) 2009 (59) 2010 (26) 2011-2013 (22) 2014-2018 (18) 2019-2023 (12)
Publication types (Num. hits)
article(105) incollection(1) inproceedings(782)
Venues (Conferences, Journals, ...)
FPL(164) FPGA(91) FCCM(58) IPDPS(36) DSD(20) ISCAS(20) IEEE Trans. Very Large Scale I...(16) DATE(15) ARC(14) ICES(13) ASAP(12) IEEE International Workshop on...(11) ISVLSI(11) AHS(10) J. VLSI Signal Process.(10) CHES(8) More (+10 of total 216)
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Found 888 publication records. Showing 888 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
62Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Virtex FPGA, runtime reconfiguration, power consumption
54Anup Kumar Raghavan, Peter Sutton JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
54Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Parimal Patel Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46S. Sukhsawas, Khaled Benkrid A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
46Edson L. Horta, John W. Lockwood Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
46Abdsamad Benkrid, Khaled Benkrid, Danny Crookes Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Abdsamad Benkrid, Khaled Benkrid, Danny Crookes A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy FCCM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Jerzy Kasperek Real Time Morphological Image Contrast Enhancement in Virtex FPGA. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
42Muzaffar Rao, Thomas Newe, Ian Andrew Grout, Avijit Mathur High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
42Liuba Slasten, Alexey Dordopulo, Igor Kaliaev, Ilya I. Levin Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs. Search on Bibsonomy PDeS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
42Amir Moradi 0001, Markus Kasper, Christof Paar Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures - An Analysis of the Xilinx Virtex-4 and Virtex-5 Bitstream Encryption Mechanism. Search on Bibsonomy CT-RSA The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
42Christian Schuck, Bastian Haetzer, Jürgen Becker 0001 Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. Search on Bibsonomy Int. J. Reconfigurable Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
42Amir Moradi 0001, Markus Kasper, Christof Paar On the Portability of Side-Channel Attacks - An Analysis of the Xilinx Virtex 4 and Virtex 5 Bitstream Encryption Mechanism. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2011 DBLP  BibTeX  RDF
42Christian Schuck, Bastian Haetzer, Jürgen Becker 0001 Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. Search on Bibsonomy ReCoSoC The full citation details ... 2010 DBLP  BibTeX  RDF
42Bradley F. Dutton, Charles E. Stroud Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. Search on Bibsonomy CATA The full citation details ... 2009 DBLP  BibTeX  RDF
42Bradley F. Dutton, Charles E. Stroud Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. Search on Bibsonomy ESA The full citation details ... 2009 DBLP  BibTeX  RDF
41E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel Power estimation approach for SRAM-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Qiang Wang, Subodh Gupta, Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
37Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal Architecture-specific packing for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
37Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Abdsamad Benkrid, Khaled Benkrid, Danny Crookes Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs. Search on Bibsonomy ICES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Li Shang, Alireza Kaviani, Kusuma Bathala Dynamic power consumption in Virtex[tm]-II FPGA family. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Jean-Luc Beuchat, Arnaud Tisserand Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Gordon J. Brebner Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. Search on Bibsonomy FCCM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony D. Fagan Implementation of (Normalised) RLS Lattice on Virtex. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
37Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino A Co-processor System with a Virtex FPGA for Evolutionary Computation. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Cesar Ortega-Sanchez, Andrew M. Tyrrell A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs. Search on Bibsonomy ICES The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Cameron Patterson High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Gordon Hollingworth, Steve Smith, Andrew M. Tyrrell Safe Intrinsic Evolution of Virtex Devices. Search on Bibsonomy Evolvable Hardware The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Roman C. Kordasiewicz, Shahram Shirani On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4
33Roman C. Kordasiewicz, Shahram Shirani On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4
33Kuan Zhou, John F. McDonald 0001 Multi-GHz SiGe design methodologies for reconfigurable computing. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CLB, virtex, FPGA, SiGe
33Tomasz S. Czajkowski, Jonathan Rose A synthesis oriented omniscient manual editor. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF virtex-e, synthesis, manual
33Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001 Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF virtex, dynamic partial reconfiguration
33Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Virtex, Compression, Decompression
33Jiri Novotný, Otto Fucík, David Antos Project of IPv6 Router with FPGA Hardware Accelerator. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Liberouter, Virtex II, FPGA, IPv6, router
33Andreas Koch A Comprehensive Prototyping-Platform for Hardware-Software Codesign. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx
33Neil Steiner, Peter M. Athanas An Alternate Wire Database for Xilinx FPGAs. Search on Bibsonomy FCCM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou Implementation of a genetic algorithm on a virtex-ii pro FPGA. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF multiplier blocks, genetic algorithm, fpga, fitness functions
29Radu Andrei Stefan, Sorin Dan Cotofana Bitstream compression techniques for Virtex 4 FPGAs. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Andreas Ehliar, Per Karlström, Dake Liu A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Mamoun F. Al-Mistarihi Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Philippe Bulens, François-Xavier Standaert, Jean-Jacques Quisquater, Pascal Pellegrin, Gaël Rouvroy Implementation of the AES-128 on Virtex-5 FPGAs. Search on Bibsonomy AFRICACRYPT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Stefan Raaijmakers, Stephan Wong Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Irwin O. Kennedy Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Bas Breijer, Filipa Duarte, Stephan Wong An OCM based shared Memory controller for Virtex 4. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Antonio Plaza Towards Real-Time Compression of Hyperspectral Images Using Virtex-II FPGAs. Search on Bibsonomy Euro-Par The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. Search on Bibsonomy AHS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Filipa Duarte, Stephan Wong Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Michael Hübner 0001, Christian Schuck, Jürgen Becker 0001 Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Carsten Bieser, Klaus D. Müller-Glaser Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Heiko Kalte, Mario Porrmann REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF bitstream manipulation, task relocation, FPGA, reconfigurable computing
29Melanie Po-Leen Ooi Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Peter J. Green, Desmond P. Taylor Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Jing Lu, John W. Lockwood IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Kyrre Glette, Jim Tørresen A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. Search on Bibsonomy ICES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi Heavy Ion Effects on Configuration Logic of Virtex FPGAs. Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis The Virtex II ProTM MOLEN Processor. Search on Bibsonomy SAMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001 Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek Post-placement C-slow retiming for the xilinx virtex FPGA. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF C-slow retiming, FPGA CAD, FPGA optimization, retiming
29Xiaojun Wang, Brent E. Nelson Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. Search on Bibsonomy FCCM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, verification, dynamic reconfiguration, run-time reconfiguration
29Matthias Dyer, Christian Plessl, Marco Platzner Partially Reconfigurable Cores for Xilinx Virtex. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Alexander Staller, Peter Dillinger, Reinhard Männer Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Trevor W. Fox, Laurence E. Turner Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Oswaldo Cadenas, Graham M. Megson A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Tim Courtney, Richard H. Turner, Roger F. Woods Multiplexer Based Reconfiguration for Virtex Multipliers. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
29Gordon Hollingworth, Steve Smith, Andy M. Tyrrell The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic. Search on Bibsonomy ICES The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu A modular NFA architecture for regular expression matching. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF character class constraint repetition, overlapped matching, FPGA, regular expression, NFA
24Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 Intel nehalem processor core made FPGA synthesizable. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF intel nehalem, synthesizable core, fpga, emulator
24Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001 A novel BIST approach for testing input/output buffers in FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF i/o buffers, built-in self-test, fpga testing
24Pramod Kumar Meher, Jagdish Chandra Patra Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. Search on Bibsonomy ASAP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Roar Lien, Tim Grembowski, Kris Gaj A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512. Search on Bibsonomy CT-RSA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
21Saber Krim, Mohamed Faouzi Mimouni Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive. Search on Bibsonomy J. Syst. Control. Eng. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21N. Sathiabama, S. Anila A Universal BIST Approach for Virtex-Ultrascale Architecture. Search on Bibsonomy Comput. Syst. Sci. Eng. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Chang Cai, Bingxu Ning, Xue Fan, Tianqi Liu, Lingyun Ke, Gengsheng Chen, Jian Yu, Ze He, Liewei Xu, Jie Liu 0032 SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs. Search on Bibsonomy Sci. China Inf. Sci. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21M. Vivekanandan, Subramanian Kanaga Suba Raja Virtex-II Pro FPGA Based Smart Agricultural System. Search on Bibsonomy Wirel. Pers. Commun. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Ahmed J. Abd El-Maksoud, Amr Gamal, Aya Hesham, Gamal Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, Hassan Mostafa Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. Search on Bibsonomy ICM The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Karan Desai, Justin Johnson 0001 VirTex: Learning Visual Representations From Textual Annotations. Search on Bibsonomy CVPR The full citation details ... 2021 DBLP  BibTeX  RDF
21Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. Search on Bibsonomy ISDCS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. Search on Bibsonomy ISNCC The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Baoju Chen, Simin Yu, Ping Chen, Liangshan Xiao, Jinhu Lü Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications. Search on Bibsonomy Int. J. Bifurc. Chaos The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Karan Desai, Justin Johnson 0001 VirTex: Learning Visual Representations from Textual Annotations. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
21Ali H. Gad, Seif Eldeen E. Abdalazeem, Omar A. Abdelmegid, Hassan Mostafa Low power and area SHA-256 hardware accelerator on Virtex-7 FPGA. Search on Bibsonomy NILES The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Abd El-Rahman Mohsen, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, Mahmoud Asy, Hassan Mostafa Remote FPGA Lab For ZYNQ and Virtex-7 Kits. Search on Bibsonomy MWSCAS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Abbas Yazdinejad, Ali Bohlooli, Kamal Jamshidi Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605. Search on Bibsonomy J. Supercomput. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Lars Engeln, Rainer Groh 0001 VirtEx: Eine Ontologie-basierte Virtuelle Ausstellungen. Search on Bibsonomy MuC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Chao Wang, Shengjun Xiong A High-precision Underwater Acoustic Communication Signal Modeling Method Based on VirTEX Algorithm. Search on Bibsonomy ICSPCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Tingting Yu, Lei Chen 0010, Xuewu Li, Shuo Wang, Jing Zhou Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA. Search on Bibsonomy IEEA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
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