Search results for "vliw"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
106	Hans M. Mulder, Robert J. Portier	Cost-effective design of application specific VLIW processors using the SCARCE framework.	MICRO	1989	DBLP DOI BibTeX RDF
103	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
103	Rahul Nagpal, Y. N. Srikant	Compiler-assisted leakage energy optimization for clustered VLIW architectures.	EMSOFT	2006	DBLP DOI BibTeX RDF	scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors
95	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP DOI BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
93	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
90	Anup Gangwar, M. Balakrishnan, Anshul Kumar	Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	performance evaluation, VLIW, ASIP, clustered VLIW processors
84	Jun Yan 0008, Wei Zhang 0002	A time-predictable VLIW processor and its compiler support.	Real Time Syst.	2008	DBLP DOI BibTeX RDF	if-conversion, Compiler, VLIW, WCET analysis, Time-predictability
84	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
84	Emre Özer 0001, Thomas M. Conte	High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Multithreaded processors, VLIW architectures, modeling of computer architecture
84	Alberto Ferreira de Souza, Peter Rounce	On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture.	IPDPS	2000	DBLP DOI BibTeX RDF	DTSVLIW, VLIW, Instruction scheduling
81	Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes	Datapath Design for a VLIW Video Signal Processor.	HPCA	1997	DBLP DOI BibTeX RDF	datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
75	Andrei Sergeevich Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
72	Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya	Performance Comparison of ILP Machines with Cycle Time Evaluation.	ISCA	1996	DBLP DOI BibTeX RDF
70	Zhixiong Zhou, Hu He 0001, Yanjun Zhang, Yihe Sun, Adriel Cheng	A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.	ASAP	2007	DBLP DOI BibTeX RDF
70	Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker	A Distributed Control Path Architecture for VLIW Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
70	Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob	Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs.	ISCA	2004	DBLP DOI BibTeX RDF
70	Marco Danelutto, Marco Vanneschi	VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors.	MICRO	1990	DBLP BibTeX RDF
69	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
69	Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio	A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
66	Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee	Enabling compiler flow for embedded VLIW DSP processors with distributed register files.	LCTES	2007	DBLP DOI BibTeX RDF	distributed register files, embedded VLIW DSP compilers, software pipelining
66	Milos Becvár, Stanislav Kahánek	VLIW-DLX simulator for educational purposes.	WCAE	2007	DBLP DOI BibTeX RDF	simulation, education, computer architecture, VLIW
66	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler optimization on VLIW instruction scheduling for low power.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
66	Xiushan Feng, Alan J. Hu	Automatic formal verification for scheduled VLIW code.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	theory of equality with uninterpreted functions, formal verification, DSP, symbolic execution, VLIW
66	Sunghyun Jee, Kannappan Palaniappan	Performance evaluation for a compressed-VLIW processor.	SAC	2002	DBLP DOI BibTeX RDF	CVLIW processor, individual instruction scheduling, VLIW, ILP
66	Sunghyun Jee, Kannappan Palaniappan	Dynamically Scheduling VLIW Instructions with Dependency Information.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP
66	Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon	Energy estimation and optimization of embedded VLIW processors based on instruction clustering.	DAC	2002	DBLP DOI BibTeX RDF	power estimation, vliw architectures
66	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
63	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
63	Soo-Mook Moon, Scott D. Carson	Generalized Multiway Branch Unit for VLIW Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, Instruction-level parallelism, superscalar microprocessor
61	Yingchao Zhao 0001, Chun Jason Xue, Minming Li, Bessie C. Hu	Energy-aware register file re-partitioning for clustered VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
61	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Cluster-level simultaneous multithreading for VLIW processors.	ICCD	2007	DBLP DOI BibTeX RDF
61	Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal	Evaluation of Speed and Area of Clustered VLIW Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
61	Pradeep Rao, S. K. Nandy 0001, M. N. V. Satya Kiran	Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
61	Christoforos E. Kozyrakis, David A. Patterson 0001	Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks.	MICRO	2002	DBLP DOI BibTeX RDF
61	Tarun Nakra, Rajiv Gupta 0001, Mary Lou Soffa	Value Prediction in VLIW Machines.	ISCA	1999	DBLP DOI BibTeX RDF
61	Wolfgang Karl	Some Design Aspects for VLIW Architectures Exploiting Fine - Grained Parallelism.	PARLE	1993	DBLP DOI BibTeX RDF
60	Kemal Ebcioglu, Erik R. Altman	DAISY: Dynamic Compilation for 100% Architectural Compatibility.	ISCA	1997	DBLP DOI BibTeX RDF	object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
57	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
57	Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee	Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	VLIW DSP processor, optimizing context switch overhead, microkernel design
57	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
57	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
57	Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	low-power-dissipation, performance, memory, VLIW processors, multi-media, code transformations, subword parallelism, system level
57	Andrei Sergeevich Terechko, Erwan Le Thenaff, Henk Corporaal	Cluster assignment of global values for clustered VLIW processors.	CASES	2003	DBLP DOI BibTeX RDF	compiler, register allocation, VLIW, instruction scheduler, ILP, cluster assignment
57	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
57	Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Branch prediction techniques for low-power VLIW processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, branch prediction, VLIW processors
57	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
57	Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte	A Fast Interrupt Handling Scheme for VLIW Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
52	Talal Bonny, Jörg Henkel	FBT: filled buffer technique to reduce code size for VLIW processors.	ICCAD	2008	DBLP DOI BibTeX RDF
52	Mario Schölzel	Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP.	DATE	2007	DBLP DOI BibTeX RDF
52	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Merge Logic for Clustered Multithreaded VLIW Processors.	DSD	2007	DBLP DOI BibTeX RDF
52	Rahul Nagpal, Y. N. Srikant	Register File Energy Optimization for Snooping Based Clustered VLIW Architectures.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
52	Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee	Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.	RTCSA	2006	DBLP DOI BibTeX RDF
52	Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee	Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files.	LCPC	2006	DBLP DOI BibTeX RDF
52	Peter Rounce, Alberto Ferreira de Souza	The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
52	Jiangjiang Liu 0002, Brian Bell, Tan Truong	Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
52	Alberto Ferrante, Giuseppe Piscopo, Stefano Scaldaferri	Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
52	Esther Salamí, Mateo Valero	A Vector-µSIMD-VLIW Architecture for Multimedia Applications.	ICPP	2005	DBLP DOI BibTeX RDF
52	Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne	Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.	SCOPES	2004	DBLP DOI BibTeX RDF
52	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
52	Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen	An Efficient VLIW DSP Architecture for Baseband Processing.	ICCD	2003	DBLP DOI BibTeX RDF
52	Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas	A code decompression architecture for VLIW processors.	MICRO	2001	DBLP DOI BibTeX RDF
52	Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung	Feedback-directed memory disambiguation for embedded multimedia VLIW computing.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
52	Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá	Synthesizing A Long Latency Unit Within Vliw Processor.	VLSI Design	2001	DBLP DOI BibTeX RDF
52	Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans	Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures.	ICCD	2000	DBLP DOI BibTeX RDF
52	Alberto Ferreira de Souza, Peter Rounce	Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
52	Monica S. Lam	Software pipelining: an effective scheduling technique for VLIW machines (with retrospective)	Best of PLDI	1988	DBLP DOI BibTeX RDF
48	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Hybrid multithreading for VLIW processors.	CASES	2009	DBLP DOI BibTeX RDF	multithreading, clustered VLIW processors
48	Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee	Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW
48	Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
48	Shu Xiao 0001, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
48	Shan Yan, Bill Lin 0001	Stream execution on wide-issue clustered VLIW architectures.	LCTES	2007	DBLP DOI BibTeX RDF	scheduling, compilers, VLIW processors, stream programming
48	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
48	Antonio Carlos Schneider Beck, Luigi Carro	A VLIW low power Java processor for embedded applications.	SBCCI	2004	DBLP DOI BibTeX RDF	Java, power consumption, VLIW
48	Binu K. Mathew, Al Davis	A loop accelerator for low power embedded VLIW processors.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, VLIW
48	Montserrat Ros, Peter Sutton	A hamming distance based VLIW/EPIC code compression technique.	CASES	2004	DBLP DOI BibTeX RDF	VLIW, hamming distance, code compression
48	Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low-power design, branch prediction, VLIW processors
48	Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon	A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.	DATE	2003	DBLP DOI BibTeX RDF	Data compression algorithms, system-level energy optimization, VLIW embedded processors
48	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	VLIW processor test, test-time analysis, Design for Testability (DfT), test synthesis
48	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	An interleaved cache clustered VLIW processor.	ICS	2002	DBLP DOI BibTeX RDF	attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
48	Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau	Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC
48	Zhao Wu, Wayne H. Wolf	Design Study of Shared Memory in VLIW Video Signal Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	VSP, stride prediction table, cache, shared memory, VLIW, trace-driven simulation, memory system, stream buffer, multi-cluster
47	Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya	Industrial experience using rule-driven retargetable code generation for multimedia applications.	ISSS	1995	DBLP DOI BibTeX RDF	VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio
45	Hai Lin 0004, Yunsi Fei	Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency.	DATE	2008	DBLP DOI BibTeX RDF
44	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	CSMT: Simultaneous Multithreading for Clustered VLIW Processors.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	clustered VLIW architectures, ILP, simultaneous multithreading, multithreaded processors, VLIW architectures
43	Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby	On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.	HPCC	2009	DBLP DOI BibTeX RDF
43	Markus Koester, Wayne Luk, Geoffrey Brown	A hardware compilation flow for instance-specific VLIW cores.	FPL	2008	DBLP DOI BibTeX RDF
43	Ihor O. Kirenko, René J. van der Vleuten, Ling Shao 0001	Optimizing Scalable Video Compression for Efficient Implementation on a VLIW Media Processor.	IEEE Trans. Multim.	2007	DBLP DOI BibTeX RDF
43	Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan	Energy Based Design Space Exploration of Multiprocessor VLIW Architectures.	DSD	2007	DBLP DOI BibTeX RDF
43	Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
43	Abhishek Pillai, Wei Zhang 0002, Dimitrios Kagaris	Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
43	Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas	Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
43	Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo	2D-VLIW: An Architecture Based on the Geometry of Computation.	ASAP	2006	DBLP DOI BibTeX RDF
43	Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	Shu Xiao 0001, Edmund Ming-Kit Lai	Instruction scheduling of VLIW architectures for balanced power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen	Hierarchical instruction encoding for VLIW digital signal processors.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
43	Andrei Sergeevich Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal	Inter-Cluster Communication Models for Clustered VLIW Processors.	HPCA	2003	DBLP DOI BibTeX RDF
43	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	An instruction-level energy model for embedded VLIW architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
43	Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui	Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture.	ICCD	2002	DBLP DOI BibTeX RDF
43	Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama	A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
43	Emre Özer 0001, Thomas M. Conte, Saurabh Sharma	Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors.	HiPC	2001	DBLP DOI BibTeX RDF