Search results for "wirelength"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
136	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang	Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.	SLIP	2003	DBLP DOI BibTeX RDF	?-geometry routing, ?-geometry-driven placement, wirelength reduction estimation
104	Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet	Faster minimization of linear wirelength for global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
83	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky	On wirelength estimations for row-based placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
75	Andrew B. Kahng, Sherief Reda	A tale of two nets: studies of wirelength progression in physical design.	SLIP	2006	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, consistency, similarity, wirelength
75	Shankar Balachandran, Dinesh Bhatia	A-priori wirelength and interconnect estimation based on circuit characteristics.	SLIP	2003	DBLP DOI BibTeX RDF	routing demand, placement, wirelength, interconnect estimation
73	Andrew B. Kahng, Sherief Reda	Wirelength minimization for min-cut placements via placement feedback.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
73	Shankar Balachandran, Dinesh Bhatia	A priori wirelength and interconnect estimation based on circuit characteristic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
73	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
73	Charles C. Chiang, Qing Su, Ching-Shoei Chiang	Wirelength reduction by using diagonal wire.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	45° routing, diagonal routing, routing, steiner tree
71	Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten	A pareto-algebraic framework for signal power optimization in global routing.	ISLPED	2010	DBLP DOI BibTeX RDF	pareto algebra, global routing, dynamic power
71	Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang	Effective Wire Models for X-Architecture Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
71	Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang	X-architecture placement based on effective wire models.	ISPD	2007	DBLP DOI BibTeX RDF	X architecture, partitioning, placement, physical design, Steiner tree, min cut, net weighting
71	Andrew B. Kahng, Qinke Wang	Implementation and extensibility of an analytic placer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
71	Tony F. Chan, Jason Cong, Kenton Sze	Multilevel generalized force-directed method for circuit placement.	ISPD	2005	DBLP DOI BibTeX RDF	force-directed method, multilevel, standard cell placement
71	Andrew B. Kahng, Qinke Wang	Implementation and extensibility of an analytic placer.	ISPD	2004	DBLP DOI BibTeX RDF	I/O-Core co-placement, hierarchical placement, congestion, geometric constraints, analytical placement
64	Alastair M. Smith, Steven J. E. Wilton, Joydip Das	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.	FPGA	2009	DBLP DOI BibTeX RDF	fpga modeling, wirelength estimation, fpga, architecture design
63	Jackey Z. Yan, Chris Chu, Wai-Kei Mak	SafeChoice: a novel clustering algorithm for wirelength-driven placement.	ISPD	2010	DBLP DOI BibTeX RDF	vlsi placement, physical design, hypergraph clustering
63	Jie Hao, Silong Peng	HJ-hPl: Hierarchical Mixed-Size Placement Algorithm with Priori Wirelength Estimation.	ICYCS	2008	DBLP DOI BibTeX RDF
63	Pradeep Fernando, Srinivas Katkoori	An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.	VLSI Design	2008	DBLP DOI BibTeX RDF
63	Jarrod A. Roy, James F. Lu, Igor L. Markov	Seeing the forest and the trees: Steiner wirelength optimization in placemen.	ISPD	2006	DBLP DOI BibTeX RDF	routing, placement, physical design, Steiner tree
63	Vyas Krishnan, Srinivas Katkoori	Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
63	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
63	Chris Chu	FLUTE: fast lookup table based wirelength estimation technique.	ICCAD	2004	DBLP DOI BibTeX RDF
63	Andrew B. Kahng, Xu Xu 0001	Accurate pseudo-constructive wirelength and congestion estimation.	SLIP	2003	DBLP DOI BibTeX RDF
63	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky	On wirelength estimations for row-based placement.	ISPD	1998	DBLP DOI BibTeX RDF
62	Stelian Alupoaei, Srinivas Katkoori	Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	net clustering, macro-cell placement, cluster growth, wirelength optimization, simulated annealing
61	Minsik Cho, David Z. Pan	BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
61	Jason Cong, Guojie Luo, Jie Wei, Yan Zhang	Thermal-Aware 3D IC Placement Via Transformation.	ASP-DAC	2007	DBLP DOI BibTeX RDF
61	Natarajan Viswanathan, Chris C. N. Chu	FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model.	ISPD	2004	DBLP DOI BibTeX RDF	net models, analytical placement, standard cell placement
61	David A. Papa, Saurabh N. Adya, Igor L. Markov	Constructive benchmarking for placement.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	placer, performance, evaluation, benchmark, comparison
54	Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout	Getting more out of Donath's hierarchical model for interconnect prediction.	SLIP	2002	DBLP DOI BibTeX RDF	Donath's wirelength estimation technique, a priori wirelength estimation, partitioning based placement
53	Vyas Krishnan, Srinivas Katkoori	Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.	VLSI Design	2008	DBLP DOI BibTeX RDF
53	Jarrod A. Roy, Igor L. Markov	Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
53	Taraneh Taghavi, Majid Sarrafzadeh	Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks.	ISVLSI	2007	DBLP DOI BibTeX RDF
53	Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Wirelength estimation based on rent exponents of partitioning and placement.	SLIP	2001	DBLP DOI BibTeX RDF
52	Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh	System Level Estimation of Interconnect Length in the Presence of IP Blocks.	ISQED	2007	DBLP DOI BibTeX RDF	Wirelength Estimation, Hierarchical Placement, Large-scale Circuits, Non-Uniform Probability Distribution, Rent's Rule, IP Blocks
51	Jason Cong, Guojie Luo	A multilevel analytical placement for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
51	Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia	Hippocrates: First-Do-No-Harm Detailed Placement.	ASP-DAC	2007	DBLP DOI BibTeX RDF	synthesis optimizations, Hippocrates, first-do-no-harm detailed placement, pin-based timing constraint, electrical constraints, reduced wire-length
51	Natarajan Viswanathan, Chris C. N. Chu	FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
51	Andrew B. Kahng, Igor L. Markov, Sherief Reda	On legalization of row-based placements.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	min-cut placement, legalization, detailed placement
51	Jason Cong, Andrew B. Kahng, Gabriel Robins	Matching-based methods for high-performance clock routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
44	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001	Optimizing wirelength and routability by searching alternative packings in floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	wirelength reduction, Floorplanning
43	Audip Pandit, Ali Akoglu	Wirelength Prediction for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
43	Chen Li 0004, Cheng-Kok Koh	Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.	ISQED	2007	DBLP DOI BibTeX RDF
43	Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke	Wirelength Reduction Using 3-D Physical Design.	PATMOS	2004	DBLP DOI BibTeX RDF
43	Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky	Optimization of Linear Placements for Wirelength Minimization with Free Sites.	ASP-DAC	1999	DBLP DOI BibTeX RDF
42	Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim	Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.	SLIP	2009	DBLP DOI BibTeX RDF	wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via
42	Pratik J. Shah, Jiang Hu	Impact of lithography-friendly circuit layout.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cd variation, lithography, wirelength, routing congestion
42	Jin-Tai Yan, Zhi-Wei Chen	RDL pre-assignment routing for flip-chip designs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	RDL routing, flip-chip design, routability, wirelength
42	Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu	Optimal cell flipping in placement and floorplanning.	DAC	2006	DBLP DOI BibTeX RDF	flipping, placement, floorplanning, orientation, wirelength
42	Yangdong Deng, Wojciech Maly	Interconnect characteristics of 2.5-D system integration scheme.	ISPD	2001	DBLP DOI BibTeX RDF	2.5-D system integration, bounded sliceline grid, VLSI, partition, placement, floorplanning, wirelength
42	Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout	On rent's rule for rectangular regions.	SLIP	2001	DBLP DOI BibTeX RDF	layout Rent parameters, rectangular layout region, wirelength distribution, Rent's rule
41	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
41	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	A novel fixed-outline floorplanner with zero deadspace for hierarchical design.	ICCAD	2008	DBLP DOI BibTeX RDF	floorplanner, soft modules, zero deadspace, fixed-outline
41	Jia-Wei Fang, Yao-Wen Chang	Area-I/O flip-chip routing for chip-package co-design.	ICCAD	2008	DBLP DOI BibTeX RDF
41	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
41	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Jason Cong, Min Xie 0004	A robust detailed placement for mixed-size IC designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
41	Yiyu Shi 0001, Paul Mesa, Hao Yu 0001, Lei He 0001	Circuit simulation based obstacle-aware Steiner routing.	DAC	2006	DBLP DOI BibTeX RDF	OARSMT, RSMT, simulation, routing
41	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
41	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Assessment of on-chip wire-length distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
41	Andrew B. Kahng, Sherief Reda	Placement feedback: a concept and method for better min-cut placements.	DAC	2004	DBLP DOI BibTeX RDF	min-cut placement, terminal propagation, feedback
41	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.	ISQED	2003	DBLP DOI BibTeX RDF
41	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001, Dirk Stroobandt	Toward better wireload models in the presence of obstacles.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
41	Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh	Congestion minimization during placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
33	Wentao Sui, Sheqin Dong, Jinian Bian	Wirelength-driven force-directed 3D FPGA placement.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	SA, partition, placement, legalization, 3-D, force-directed
33	Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji	Near-linear wirelength estimation for FPGA placement.	CCECE	2009	DBLP DOI BibTeX RDF
33	Stelian Alupoaei, Srinivas Katkoori	Energy Model Based Macrocell Placement for Wirelength Minimization.	VLSI Design	2004	DBLP DOI BibTeX RDF
32	Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi	Quantified Impacts of Guardband Reduction on Design Process Outcomes.	ISQED	2008	DBLP DOI BibTeX RDF	Guardband, chip size, yield, runtime, wirelength, design iterations
32	Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh	Tutorial on congestion prediction.	SLIP	2007	DBLP DOI BibTeX RDF	algorithm, prediction, delay, congestion, wirelength
32	Chris C. N. Chu, Yiu-Chung Wong	Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design.	ISPD	2005	DBLP DOI BibTeX RDF	rectilinear steiner minimal tree algorithm, wirelength estimation, routing
32	Shyam Ramji, Nagu R. Dhanwada	Design topology aware physical metrics for placement analysis.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	path-monotonicity, placement, timing analysis, wirelength
31	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
31	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan	BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	VLSI, physical design, congestion, integer linear programming, global routing, routability, layer assignment
31	Jin-Tai Yan, Zhi-Wei Chen	IO connection assignment and RDL routing for flip-chip designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
31	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Jason Cong, Min Xie 0004	A Robust Mixed-Size Legalization and Detailed Placement Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Song Chen 0001, Takeshi Yoshimura	Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan	Guiding global placement with wire density.	ICCAD	2008	DBLP DOI BibTeX RDF
31	Seungwhun Paik, Youngsoo Shin	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.	DAC	2008	DBLP DOI BibTeX RDF	sleep vector, zigzag power gating, low power, leakage current, standard-cell
31	Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-Driven Placement and White Space Allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
31	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan	BoxRouter 2.0: architecture and implementation of a hybrid and robust global router.	ICCAD	2007	DBLP DOI BibTeX RDF
31	Brent Goplen, Sachin S. Sapatnekar	Placement of 3D ICs with Thermal and Interlayer Via Considerations.	DAC	2007	DBLP DOI BibTeX RDF
31	Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu	RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.	DAC	2007	DBLP DOI BibTeX RDF
31	Yiyu Shi 0001, Tong Jing, Lei He 0001, Zhe Feng 0002, Xianlong Hong	CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.	ASP-DAC	2006	DBLP DOI BibTeX RDF
31	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.	ICCAD	2006	DBLP DOI BibTeX RDF
31	Minsik Cho, David Z. Pan	BoxRouter: a new global router based on box expansion and progressive ILP.	DAC	2006	DBLP DOI BibTeX RDF	VLSI, congestion, global routing
31	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	Routing-aware scan chain ordering.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	testing, Layout, scan chain
31	Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim	Wire congestion and thermal aware 3D global placement.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Register placement for low power clock network.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
31	Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen	Multilevel full-chip routing for the X-based architecture.	DAC	2005	DBLP DOI BibTeX RDF	Xarchitecture, routing, physical design, multilevel optimization
31	Gang Chen 0020, Jason Cong	Simultaneous Timing Driven Clustering and Placement for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
31	Andrew B. Kahng, Qinke Wang	An analytic placer for mixed-size placement and timing-driven placement.	ICCAD	2004	DBLP DOI BibTeX RDF
31	Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze	An Enhanced Multilevel Algorithm for Circuit Placement.	ICCAD	2003	DBLP DOI BibTeX RDF
31	Rishi Chaturvedi, Jiang Hu	A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.	ICCD	2003	DBLP DOI BibTeX RDF
31	Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh	Flow-Based Cell Moving Algorithm for Desired Cell Distribution.	ICCD	2003	DBLP DOI BibTeX RDF
31	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Pattern routing: use and theory for increasing predictability andavoiding coupling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
31	Chung-Wen Albert Tsao, Cheng-Kok Koh	UST/DME: a clock tree router for general skew constraints.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Useful Skew, feasible skew range, incremental skew scheduling, merging and embedding, merging region, clock tree