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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1025 occurrences of 520 keywords
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Results
Found 1550 publication records. Showing 1550 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
A multiplier generator for Xilinx FPGAs. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs |
53 | Bernard Laurent, Gilles Bosco, Gabriele Saucier |
Fast Arithmetic on Xilinx 5200 FPGA. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
(do not appear on the paper): Arithmetic, Xilinx 5200 FPGA, Performance, Place and route |
50 | Anup Kumar Raghavan, Peter Sutton |
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration |
46 | Parimal Patel |
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Michael A. Shanblatt, Brian Foulds, Patrick Kane, Anna Acevedo |
A University-based Web Resource Supporting the Xilinx University Program. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Michael A. Shanblatt, Brian Foulds, Patrick Kane |
A University-Based Support Environment for the Xilinx University Program. |
MSE |
2001 |
DBLP DOI BibTeX RDF |
|
46 | Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao |
A Technology Mapper for Xilinx FPGAs. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
39 | Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001 |
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
39 | S. W. Song 0002, J. D. Zheng, William B. Gardner |
Prototyping a Residential Gateway Using Xilinx ISE. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Jean-Baptiste Note, Éric Rannaud |
From the bitstream to the netlist. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
bitstream format, FPGA, reverse-engineering |
36 | Roman C. Kordasiewicz, Shahram Shirani |
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4 |
36 | Roman C. Kordasiewicz, Shahram Shirani |
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4 |
36 | Sudip K. Nag, Rob A. Rutenbar |
Performance-driven simultaneous place and route for island-style FPGAs. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout |
36 | Hardy J. Pottinger, Chien-Yuh Lin |
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education |
35 | Wissem Chouchene |
Vers une reconfiguration dynamique partielle parallèle par prise en compte de la régularité des architectures FPGA-Xilinx. (Towards a parallel partial dynamic reconfiguration by taking into account the regularity of FPGA-Xilinx architectures). |
|
2017 |
RDF |
|
35 | Belgacem Babba |
Synthèse optimisée sur les réseaux programmables de la famille Xilinx. (Optimized Logical Synthesis on Programmable Devices of Xilinx FPGAs). |
|
1995 |
RDF |
|
32 | George Kiokes, Nikolaos K. Uzunoglu |
Development of a simulation Environment for Vehicular communications, implementation of FEC coding chain in Xilinx FPGA based on IEEE 802.11p standard. |
WOWMOM |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Leos Kafka |
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele |
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Rainer Scholz |
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford |
Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
32 | David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001 |
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. |
FCCM |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter |
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Trevor W. Fox, Laurence E. Turner |
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch |
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Xinyu Li, Omar Hammami |
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, multiprocessor, network on chip |
29 | Hui Qin, Tsutomu Sasao, Jon T. Butler |
Implementation of LPM Address Generators on FPGAs. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier |
Adaptive Fault Recovery for Networked Reconfigurable Systems. |
FCCM |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu |
Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System. |
ICA3PP |
2009 |
DBLP DOI BibTeX RDF |
Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication |
29 | Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie |
CReconfigurable finite field instruction set architecture. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
MicroBlaze, embedded development, fast simplex links, galois fields, instruction set extensions, partial reconfiguration, finite field arithmetic, Xilinx, FSL |
29 | Choudhury A. Rahman, Wael M. Badawy |
A quarter pel full search block motion estimation architecture for H.264/AVC. |
ICME |
2005 |
DBLP DOI BibTeX RDF |
CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL |
29 | Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins |
Compiling and Optimizing Image Processing Algorithms for FPGAs. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms |
29 | Abderrahim Doumar, Hideo Ito |
Testing approach within FPGA-based fault tolerant systems. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase |
29 | Andreas Koch |
A Comprehensive Prototyping-Platform for Hardware-Software Codesign. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx |
29 | Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor |
FPGA-Based Structures for On-Line FFT and DCT. |
FCCM |
1999 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic |
29 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
29 | R. Maheshwari, S. S. S. P. Rao, E. G. Poonach |
FPGA Implementation of Median Filter. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
real time median filter, Xilinx XC4010 FPGA chip, field programmable gate arrays, design, algorithm, sliding window |
29 | Adam Postula, David Abramson 0001, Paul Logothetis |
The Design of a Specialised Processor for the Simulation of Sintering A. Postula. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
specialised processor, sintering simulation, metallurgical sintering, commercially available gate array technology, Xilinx FPGA, Aptix FPIC switch technology, FPGAs, Monte-Carlo simulation, special purpose computers |
29 | Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover |
FPGA-based high performance page layout segmentation. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
Splash 2, page layout segmentation algorithm, FPGA array processor, Xilinx synthesis tool, 5 GHz, 1024 pixel, field programmable gate arrays, image segmentation, parallel processing, text |
29 | Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi |
On the diagnosis of programmable interconnect systems: Theory and application. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections |
29 | Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001 |
Re-engineering of timing constrained placements for regular architectures. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging |
25 | Alexander Klimm, Oliver Sander, Jürgen Becker 0001 |
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Gabriel Lizárraga, Roberto Sepúlveda, Oscar Montiel, Oscar Castillo 0001 |
Modeling and Simulation of the Defuzzification Stage Using Xilinx System Generator and Simulink. |
Soft Computing for Hybrid Intelligent Systems |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo 0001 |
Design and Simulation of the Fuzzification Stage through the Xilinx System Generator. |
Soft Computing for Hybrid Intelligent Systems |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001 |
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Mamoun F. Al-Mistarihi |
Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Katarina Paulsson, Michael Hübner 0001, Günther Auer, Michael Dreschmann, Jürgen Becker 0001 |
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid |
A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Filipa Duarte, Stephan Wong |
Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Go-An Rau, Meng-Xin Guo |
Multiplierless Realization of Modified Comb Filter by Using Xilinx Spartan FPGAs. |
ICICIC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio |
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Carsten Bieser, Klaus D. Müller-Glaser |
Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Min-Hong Chen, Feng-Cheng Chang, Hsueh-Ming Hang |
Design and Implementation of an MHP Video and Graphics Subsystem on Xilinx ML310 Platform. |
IIH-MSP |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Melanie Po-Leen Ooi |
Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Peter J. Green, Desmond P. Taylor |
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Ana Toledo Moreo, Cristina Vicente-Chicote, Juan Suardíaz Muro, Sergio A. Cuenca |
Xilinx System Generator Based HW Components for Rapid Prototyping of Computer Vision SW/HW Systems. |
IbPRIA (1) |
2005 |
DBLP DOI BibTeX RDF |
FPGAs, prototyping, Simulink, co-simulation, image processing applications |
25 | Jing Lu, John W. Lockwood |
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Kyrre Glette, Jim Tørresen |
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. |
ICES |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Neil Steiner, Peter M. Athanas |
An Alternate Wire Database for Xilinx FPGAs. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
25 | J. Chandran, R. Kaluri, Jugdutt Singh, Viktor Öwall, Ronny Veljanovski |
Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek |
Post-placement C-slow retiming for the xilinx virtex FPGA. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
C-slow retiming, FPGA CAD, FPGA optimization, retiming |
25 | Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann |
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
Virtex FPGA, runtime reconfiguration, power consumption |
25 | Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson |
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
FPGA, verification, dynamic reconfiguration, run-time reconfiguration |
25 | Matthias Dyer, Christian Plessl, Marco Platzner |
Partially Reconfigurable Cores for Xilinx Virtex. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Xiaoling Sun, Jian Xu, Pieter M. Trouborst |
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
configurable logic blocks, fault diagnosis, BIST, FPGA testing |
25 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, iterative testing |
25 | Steve Guccione |
Run-Time Reconfiguration at Xilinx. |
IPDPS Workshops |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Scott Hauck, Zhiyuan Li 0008, Eric J. Schwabe |
Configuration compression for the Xilinx XC6200 FPGA. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Reiner W. Hartenstein, Michael Herz, Frank Gilbert |
Designing for Xilinx XC6200 FPGAs. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Scott Hauck, Zhiyuan Li 0008, Eric J. Schwabe |
Configuration Compression for the Xilinx XC6200 FPGA. |
FCCM |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Bradley Oraw, Vijay Choudhary, Raja Ayyanar |
A cosimulation approach to model-based design for complex power electronics and digital control systems. |
SCSC |
2007 |
DBLP BibTeX RDF |
Saber, automatic code generation, Simulink, cosimulation, digital control |
22 | Wim Roelandts |
Creating a Culture of Innovation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Yu-Pin Chang, Kai-Sheng Yang, Chao-Tang Yu |
Improved channel codec implementation and performance analysis of OFDM based DAB systems. |
IWCMC |
2006 |
DBLP DOI BibTeX RDF |
DAB, Eureka-147, OFDM, fading channel, multi-path |
22 | Bo Yang 0010, Nikhil Joshi, Ramesh Karri |
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Roar Lien, Tim Grembowski, Kris Gaj |
A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512. |
CT-RSA |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang |
Energy-efficient signal processing using FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation |
22 | Henry Styles, Wayne Luk |
Accelerating Radiosity Calculations Using Reconfigurable Platforms. |
FCCM |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Radhika S. Grover, Weijia Shang, Qiang Li |
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Delon Levi, Steve Guccione |
GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices. |
Evolvable Hardware |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Craig P. Steffen, Gildas Genest |
Nallatech In-Socket FPGA Front-Side Bus Accelerator. |
Comput. Sci. Eng. |
2010 |
DBLP DOI BibTeX RDF |
Xeon, Field-programmable gate arrays, compiler, reconfigurable, bandwidth, accelerators, Xilinx |
21 | Hesham Abdel Slam Aly Elzouka |
FPGA Based Implementation of Robust Watermarking System. |
ITNG |
2008 |
DBLP DOI BibTeX RDF |
Electronic Watermarking, Xilinx FPGA, Embedding Systems, Cryptography |
21 | Jörg Ritter 0002, Paul Molitor |
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression |
21 | Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
On Routability Prediction for Field-Programmable Gate Arrays. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
XILINX 3000 |
21 | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Sequential Synthesis for Table Look Up Programmable Gate Arrays. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
XILINX 3000 |
17 | Lucas Leiva, Bruno Constanzo, Martín Vázquez 0001, Juan Manuel Toloza |
Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU. |
IEEE Embed. Syst. Lett. |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Maik Ender, Felix Hahn, Marc Fyrbiak, Amir Moradi 0001, Christof Paar |
JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Apoorva Banerjee |
Intelligent Traffic Light Controller using Verilog and Xilinx Spartan-3e. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Maik Ender, Felix Hahn, Marc Fyrbiak, Amir Moradi 0001, Christof Paar |
JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. |
IACR Trans. Cryptogr. Hardw. Embed. Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Bardia Babaei, Dirk Koch |
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
17 | Colin Horne, Nial Peters, Matthew Ritchie |
Classification of LoRa Signals With Real-Time Validation Using the Xilinx Radio Frequency System-on-Chip. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Ihsan Çiçek, Ahmad Alkhas |
A new read-write collision-based SRAM PUF implemented on Xilinx FPGAs. |
J. Cryptogr. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Salah S. Harb, M. Omair Ahmad, M. N. S. Swamy |
An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform. |
J. Real Time Image Process. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Wafa Gtifa, Anis Sakly |
Integrating Xilinx FPGA and intelligent techniques for improved precision in 3D brain tumor segmentation in medical imaging. |
J. Real Time Image Process. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Muhammad Awais, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali |
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs. |
ACM Trans. Embed. Comput. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Jie Lei, José Flich, Enrique S. Quintana-Ortí |
Toward matrix multiplication for deep learning inference on the Xilinx Versal. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Saber Krim, Mohamed Faouzi Mimouni |
Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive. |
J. Syst. Control. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Jie Lei, José Flich, Enrique S. Quintana-Ortí |
Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal. |
PDP |
2023 |
DBLP DOI BibTeX RDF |
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