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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 699 publication records. Showing 699 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Bardia Babaei, Dirk Koch |
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices.  |
ARC  |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Minoru Watanabe |
Analysis of Clock Tree Buffer Degradation Caused by Radiation. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Torben Kalkhof, Carsten Heinz, Andreas Koch 0001 |
Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon |
Secure eFPGA Configuration: A System-Level Approach. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan Strobl, Leonardo Solis-Vasquez, Yannick Lavan, Andreas Koch 0001 |
Graphtoy: Fast Software Simulation of Applications for AMD's AI Engines. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem |
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández 0001 |
A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Mpakos, Ioanna Tasou, Chloe Alverti, Panagiotis Miliadis, Pavlos Malakonakis, Dimitris Theodoropoulos, Georgios I. Goumas, Dionisios N. Pnevmatikatos, Nectarios Koziris |
Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Iouliia Skliarova, Piedad Brox Jiménez, Mário P. Véstias, Pedro C. Diniz (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox |
Cryptographic Security Through a Hardware Root of Trust. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Meloni, Paola Busia, Gianluca Leone, Luca Martis, Matteo Antonio Scrugli |
Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Olle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez |
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sergio A. Pertuz 0001, Cornelia Wulf, Najdet Charaf, Lester Kalms, Diana Göhringer |
A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Asmita Adhikary, Abraham Basurto, Lejla Batina, Ileana Buhan, Joan Daemen, Silvia Mella, Nele Mentens, Stjepan Picek, Durga Lakshmi Ramachandran, Abolfazl Sajadi, Todor Stefanov, Dennis Vermoen, Nusa Zidaric |
PROACT - Physical Attack Resistance of Cryptographic Algorithms and Circuits with Reduced Time to Market. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Shine Parekkadan Sunny, Satyajit Das |
Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino 0001, João Bispo |
A DSL and MLIR Dialect for Streaming and Vectorisation. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Guilherme Silva 0006, Pedro Silva 0004, Gladston Moreira, Eduardo Luz 0001 |
Bridging the Gap in ECG Classification: Integrating Self-supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware Constraints. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Mira, Jesús Barba, Julián Caba, José Antonio de la Torre, Fernando Rincón, Soledad Escolar, Juan Carlos López 0001 |
High Performance Connected Components Accelerator for Image Processing in the Edge. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Murat Isik, Hiruna Vishwamith, Yusuf Sur, Kayode Inadagbo, I. Can Dikmen |
NEUROSEC: FPGA-Based Neuromorphic Audio Security. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Henrique B. Brum, Mário P. Véstias, Horácio C. Neto |
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | An Braeken, Bruno da Silva 0001, Laurent Segers, Johannes Knödtel, Marc Reichenbach, Cornelia Wulf, Sergio A. Pertuz 0001, Diana Göhringer, Jo Vliegen, Md Masoom Rabbani, Nele Mentens |
Trusted Computing Architectures for IoT Devices. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze |
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. |
ARC |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Masayuki Usui, Shinya Takamaeda-Yamazaki |
High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara |
A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Sajjad Tamimi, Arthur Bernhardt, Florian Stock, Ilia Petrov 0001, Andreas Koch 0001 |
NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Bijin Elsa Baby, Dipika Deb, Benuraj Sharma, Kirthika Vijayakumar, Satyajit Das |
Energy Efficient DNN Compaction for Edge Deployment. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni |
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake |
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Julian Haase, Diana Göhringer |
Simulation and Modelling for Network-on-Chip Based MPSoC. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Rafael Fão de Moura, Luigi Carro |
Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien |
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Gehrunger, Christian Hochberger |
Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Núñez-Yáñez |
Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Mousouliotis, Topi Leppänen, Pekka Jääskeläinen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros |
On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangelia Konstantopoulou, George Athanasiou, Nicolas Sklavos 0001 |
Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Safdar Mahmood, Michael Hübner 0001, Marc Reichenbach |
A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Marc Reichenbach |
TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez |
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej Baczmanski, Mateusz Wasala, Tomasz Kryjak |
Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniele Passaretti, Thilo Pionteck |
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Francesca Palumbo, Georgios Keramidas, Nikolaos S. Voros, Pedro C. Diniz (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Lester Kalms, Matthias Nickel, Diana Göhringer |
ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp Grothe, Saleh Mulhem, Mladen Berekovic |
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Lukas Unger, Jürgen Becker 0001, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart |
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | George Pagonis, Vasileios Leon, Dimitrios Soudris, George Lentaris |
Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá |
Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach |
More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Lennart Clausing, Zakarya Guettatfi, Paul Kaufmann, Christian Lienen, Marco Platzner |
On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaden M. Alismail, Dirk Koch |
Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Srivatsan Chandrasekar, Siew-Kei Lam, Srikanthan Thambipillai |
DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator. |
ARC |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Miliadis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Nectarios Koziris |
VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Michal Danilowicz, Tomasz Kryjak |
Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Bowen P. Y. Kwan, Ce Guo, Wayne Luk, Peiyong Jiang |
Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | David Volz, Christoph Spang 0001, Andreas Koch 0001 |
IPEC: Open-Source Design Automation for Inter-Processing Element Communication. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Philippos Papaphilippou, Myrtle Shah |
FPGA-Extended General Purpose Computer Architecture. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Yuan, Qiang Liu, Quan Deng, Shengye Xiang, Lin Gan, Jinzhe Yang, Xiaohui Duan, Haohuan Fu, Guangwen Yang |
FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Rognlien, Zhiqiang Que, José Gabriel F. Coutinho, Wayne Luk |
Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Majed Alsharari, Lorenzo Niemitz, Simon Sorensen, Roger F. Woods, Ray Burke, Stefan Andersson-Engels, Carlos Reaño, Son T. Mai |
Multi-spectral In-Vivo FPGA-Based Surgical Imaging. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Minxuan Kong, José Luis Núñez-Yáñez |
Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Laserna, Andrés Otero, Eduardo de la Torre |
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuesen Chu, He Xiang, Li Fang, Liu Zhao, Guangwen Yang |
Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Gan, Yu Wang, Wei Xue, Thomas Chau 0001 (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 18th International Symposium, ARC 2022, Virtual Event, September 19-20, 2022, Proceedings |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Omidian, Eddie Hung, Dinesh Gaitonde |
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan Kabir, Arpan Poudel, Zeyad Aklah, Miaoqing Huang, David Andrews 0001 |
A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA. |
ARC |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Carsten Heinz, Andreas Koch 0001 |
Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich |
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Jungblut, Dieter Kranzlmüller |
Dynamic Spatial Multiplexing on FPGAs with OpenCL. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Irfan 0004, Kizheppatt Vipin, Ray C. C. Cheung |
On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-Mei Hwu, Deming Chen |
Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Angela Gonzalez Mariño, Francesc Fons, Li Ming, Juan-Manuel Moreno Aróstegui |
PDU Normalizer Engine for Heterogeneous In-Vehicle Networks in Automotive Gateways. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Bosch, Miquel Vidal, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell, Eduard Ayguadé |
Task-Based Programming Models for Heterogeneous Recurrent Workloads. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck |
StreamGrid - An AXI-Stream-Compliant Overlay Architecture. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener |
Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed W. Hassan, Peter M. Athanas, Yasser Y. Hanafy |
Domain-Specific Modeling and Optimization for Graph Processing on FPGAs. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Randa Zarrouk, Saleh Mulhem, Wael Adi, Mladen Berekovic |
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy |
Hardware Based Loop Optimization for CGRA Architectures. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Arjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl |
Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Ebrahim, Jalal Khalifat |
Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable Accelerator. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Hector Gerardo Muñoz Hernandez, Mitko Veleski, Marcelo Brandalero, Michael Hübner 0001 |
Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabian Lesniak, Fabian Kreß, Jürgen Becker 0001 |
Transparent Near-Memory Computing with a Reconfigurable Processor. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jörg Keller 0001, Sebastian Litzinger, Christoph W. Kessler |
Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Linus Witschen, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, Marco Platzner |
Timing Optimization for Virtual FPGA Configurations. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Nelson Campos, Slava Chesnokov, Eran A. Edirisinghe, Alexis Lluis |
FPGA Implementation of Custom Floating-Point Logarithm and Division. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Pfau, Peter Wagih Zaki, Jürgen Becker 0001 |
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Danopoulos, Christoforos Kachris, Dimitrios Soudris |
Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Anantharajaiah, Zhe Zhang, Jürgen Becker 0001 |
Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Nadir Khan, Benjamin Hettwer, Jürgen Becker 0001 |
Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Wirth 0002, Jaco A. Hofmann, Lasse Thostrup, Andreas Koch 0001, Carsten Binnig |
Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jesús Barba, Julián Caba, Soledad Escolar, José Antonio de la Torre, Fernando Rincón, Juan C. López 0001 |
A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation. |
ARC |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck |
Optimising Operator Sets for Analytical Database Processing on FPGAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Hector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero, Michael Hübner 0001 |
A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno Ferres, Olivier Muller, Frédéric Rousseau 0001 |
Chisel Usecase: Designing General Matrix Multiply for FPGA. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ludovica Bozzoli, Luca Sterpone |
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera |
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre |
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Ali 0010, Pedram Amini Rad, Diana Göhringer |
RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano |
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Federico Favaro, Ernesto Dufrechou, Pablo Ezzatti, Juan P. Oliver |
Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhewen Yu, Christos-Savvas Bouganis |
A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
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