Search results for "ARVLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	K. Joseph Hass, Jack Venbrux, Prakash Bhatia	Logic Design Considerations for 0.5-Volt CMOS.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Alberto Pesavento, Christof Koch	Methods and Circuits for Focal-Plane Computation of Features in CMOS Visual Sensors.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Marc Cohen, Gert Cauwenberghs, Mikhail A. Vorontsov, Gary Carhart	Focal-Plane Image and Beam Quality Sensors for Adaptive Optics.	ARVLSI	2001	DBLP DOI BibTeX RDF
1		19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA	ARVLSI	2001	DBLP BibTeX RDF
1	Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee	Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Chan-Ho Park, Byung-Soo Choi, Dong-Ik Lee, Ho-Yong Choi	Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Rajit Manohar, Mika Nyström, Alain J. Martin	Precise Exceptions in Asynchronous Processors.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Oliver Landolt, Ania Mitros, Christof Koch	Visual Sensor with Resolution Enhancement by Mechanical Vibrations.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Vincent F. Koosh, Rodney M. Goodman	Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Kip C. Killpack, Eric Mercer, Chris J. Myers	A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	V. A. Bartlett, Eckhard Grass	A Low-Power Asynchronous VLSI FIR Filter.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown	Dynamic Receiver Biasing For Inter-Chip Communication.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Matt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson	Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Rajit Manohar	Width-Adaptive Data Word Architectures.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel	Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Sree Ganesan, Ranga Vemuri	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Thaddeus Gabara	Phantom Mode Signaling in VLSI Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Bruce R. Childers, Jack W. Davidson	Architectural Considerations for Application-Specific Counterflow Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Application-specific integrated processors, counterflow pipelines, architectural synthesis
1	Li-Rong Zheng 0001, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
1	John Poulton	Problems and Prospects for Electrical Signaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Neil Weste	Who Put the Sugar in Sydney Harbor?.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath	The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Charles L. Britton Jr., R. J. Warmack, Stephen F. Smith, Alan L. Wintenberg, T. Thundat, G. M. Brown, W. L. Bryan, J. C. Depriest, M. Nance Ericson, M. S. Emery, Michael Roy Moore, G. W. Turner, Lloyd G. Clonts, R. L. Jones, T. D. Threatt, Z. Hu, James M. Rochelle	Battery-powered, Wireless MEMS Sensors for High-Sensitivity Chemical and Biological Sensing.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
1	Charles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth	A Two-Dimensional, Object-Based Analog VLSI Visual Attention System.	ARVLSI	1999	DBLP DOI BibTeX RDF	attention, analog VLSI, neuromorphic, focal plane
1	Robert W. Brodersen	System-on-a-Chip VLSI - Is It Finally Really Here?	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta	A Column-based Processing Array for High-speed Digital Image Processing.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang	Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Charles M. Higgins, Christof Koch	Multi-Chip Neuromorphic Motion Processing.	ARVLSI	1999	DBLP DOI BibTeX RDF	vision chip, AER, motion, disparity, neuromorphic
1	Sudip Chakrabarti, Abhijit Chatterjee	Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	fault diagnosis, analog, Design automation, mixed-signal, fault isolation
1	William J. Dally, Steve Lacy	VLSI Architecture: Past, Present, and Future.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
1	Kwabena Boahen 0001	A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips.	ARVLSI	1999	DBLP DOI BibTeX RDF	Address-Events, Retinomorphic, VLSI, TDMA, Spiking Neurons, CMOS Imager, Neuromorphic
1	Vijay Sundararajan, Keshab K. Parhi	Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.	ARVLSI	1999	DBLP DOI BibTeX RDF	Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
1	B. E. Duewer, John M. Wilson 0002, D. A. Winick, Paul D. Franzon	MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.	ARVLSI	1999	DBLP DOI BibTeX RDF	Variable Capacitors, Programable Interconnect, RF Switching, Digital Switching, Bistable Devices, MEMS, Crossbar, Capacitive Coupling
1	Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl	Exploring Microprocessor Architectures for Gigascale Integration.	ARVLSI	1999	DBLP DOI BibTeX RDF	Billion Transistor, Future Tecnologies, Architecture, Microprocessors
1	Bradley A. Minch	Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Timothy K. Horiuchi, Ernst Niebur	Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
1	Paul E. Hasler, Bradley A. Minch, Chris Diorio	Adaptive Circuits Using pFET Floating-Gate Devices.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Ramakrishna Voorakaranam, Abhijit Chatterjee	Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.	ARVLSI	1999	DBLP DOI BibTeX RDF	analog verification, fault diagnosis, test generation, analog testing, Backtrace
1	Sek M. Chai, Antonio Gentile, D. Scott Wills	Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.	ARVLSI	1999	DBLP DOI BibTeX RDF	billion-transistor, image processing, technology, SIMD, system modeling, parallel computer architecture, Power density, focal plane
1	Sandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci	Area-Universal Circuits with Constant Slowdown.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling	Architecture Design of Reconfigurable Pipelined Datapaths.	ARVLSI	1999	DBLP DOI BibTeX RDF	High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing
1	Spencer M. Gold, Richard B. Brown, Bruce Bernhardt	A Quantitative Approach to Nonlinear Process Design Rule Scaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Charles L. Seitz	Silicon Adventures-Go Ahead; Be Bold!	ARVLSI	1999	DBLP DOI BibTeX RDF
1		18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA	ARVLSI	1999	DBLP BibTeX RDF
1	James D. Meindl	XXI Century Gigascale Integration (GSI) : The Interconnect Problem.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Les Hall, Mark Clements, Wentai Liu, Griff L. Bilbro	Clock Distribution Using Cooperative Ring Oscillators.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
1	Martin Benes 0002, Andrew Wolfe, Steven M. Nowick	A High-Speed Asynchronous Decompression Circuit for Embedded Processors.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Kevin J. Nowka, H. Peter Hofstee	Circuits and Microarchitecture for Gigahertz VLSI Designs.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	John Poulton	An Embedded DRAM for CMOS ASICs.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Alejandro F. González, Pinaki Mazumder	Compact Signed-Digit Adder Using Multiple-Valued Logic.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	David Parry 0001	Scalability in computing for today and tomorrow.	ARVLSI	1997	DBLP DOI BibTeX RDF	synergistic combination, performance growth, current multiprocessor alternatives, scalable SMP, Silicon Graphics Origin multiprocessor, S/sup 2/MP memory architecture, core technologies, scalability, system architecture, shared-memory multiprocessors, shared memory systems
1	Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi	Design Implementation of Intrinsic Area Array ICs.	ARVLSI	1997	DBLP DOI BibTeX RDF	Area-array pad, flip-chip, physical design, VLSI design, placement and routing
1		17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA	ARVLSI	1997	DBLP BibTeX RDF
1	Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese	A VLSI Architecture for Modeling Intersegmental Coordination.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Todd Hinck, Allyn E. Hubbard	Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing.	ARVLSI	1997	DBLP DOI BibTeX RDF	Silicon Retina, Image Edge Enhancement, Neural Network, Spatial Filtering, Analog VLSI
1	Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings	The Design of an Asynchronous MIPS R3000 Microprocessor.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun	The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Allen E. Sjogren, Chris J. Myers	Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline.	ARVLSI	1997	DBLP DOI BibTeX RDF	Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure
1	V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi	Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity.	ARVLSI	1997	DBLP DOI BibTeX RDF	Coupled interconnects, Distributed lines, Proximity effects, Interconnect delay, Moment matching
1	Behzad Razavi	Next-Generation RF Circuits and Systems.	ARVLSI	1997	DBLP DOI BibTeX RDF	RF circuits, RF systems, wireless local loops, RF identification devices, multi-standard transceivers, IC technologies, wireless LAN, wireless LAN, wireless local area networks, CAD tools, cable modems
1	Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai	Architectural Design of a Three Dimensional FPGA.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Nathan Shnidman, William H. Mangione-Smith, Miodrag Potkonjak	Fault Scanner for Reconfigurable Logic.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis	Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control
1	Hans M. Jacobson, Ganesh Gopalakrishnan	Asynchronous Microengines for Efficient High-level Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	asynchronous circuits, microprogramming, self-timing
1	David M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey	Kestrel: Design of an 8-bit SIMD Parallel Processor.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Daniel W. Dobberpuhl	Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Erik Brunvand	Low latency self-timed flow-through FIFOs.	ARVLSI	1995	DBLP DOI BibTeX RDF	self-timed flow-through FIFO, linear flow-through FIFO, parallel FIFO, tree FIFO, square FIFO, folded FIFO, low latency type, field programmable gate arrays, VLSI, asynchronous circuits, CMOS logic circuits
1	Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick	Algorithms for the optimal state assignment of asynchronous state machines.	ARVLSI	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic
1	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
1	Gill A. Pratt, John Nguyen	Distributed synchronous clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals
1	Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos	Low-latency plesiochronous data retiming.	ARVLSI	1995	DBLP DOI BibTeX RDF	telecommunication signalling, data retiming, plesiochronous data, support circuitry, undirectional signalling, timing, latency, communication networks, routers, telecommunication network routing, repeaters, repeaters, bridges, hubs
1	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
1	Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst	Silicon VLSI processing architectures incorporating integrated optoelectronic devices.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
1	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
1	Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum	Standard CMOS active pixel image sensors for multimedia applications.	ARVLSI	1995	DBLP DOI BibTeX RDF	CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain
1		16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA	ARVLSI	1995	DBLP BibTeX RDF
1	John Lazzaro, John Wawrzynek	A multi-sender asynchronous extension to the AER protocol.	ARVLSI	1995	DBLP DOI BibTeX RDF	multi-sender extension, AER, address-event representation, asynchronous point-to-point communications protocol, silicon neural systems, protocols, neural chips
1	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
1	Stan Y. Liao, Srinivas Devadas, Kurt Keutzer	Code density optimization for embedded DSP processors using data compression techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	code density optimization, embedded DSP processors, code size minimization, text compression algorithms, TMS320C25 code generator, VLSI, data compression, data compression, skeleton, minimisation, dictionary, digital signal processing chips, VLSI systems, production cost
1	Hans Lindkvist, Per Andersson	Dynamic CMOS circuit techniques for delay and power reduction in parallel adders .	ARVLSI	1995	DBLP DOI BibTeX RDF	dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
1	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
1	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
1	Timothy J. Stanley, Trevor N. Mudge	Systematic objective-driven computer architecture optimization.	ARVLSI	1995	DBLP DOI BibTeX RDF	objective-driven optimization, microarchitectural configuration, directed search problem, genetic algorithms, genetic algorithm, CAD, computer-aided design, computer architecture, computer architecture, memory hierarchy, search problems, memory architecture, dimensionality
1	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
1	Kumar N. Lalgudi, Marios C. Papaefthymiou	Efficient retiming under a general delay model.	ARVLSI	1995	DBLP DOI BibTeX RDF	retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
1	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
1	Huy Nguyen 0001, Abhijit Chatterjee	OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.	ARVLSI	1995	DBLP DOI BibTeX RDF	linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition
1	Gert Cauwenberghs	Bit-serial bidirectional A/D/A conversio.	ARVLSI	1995	DBLP DOI BibTeX RDF	digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
1	X. Cai, Keith Nabors, Jacob K. White 0001	Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics.	ARVLSI	1995	DBLP DOI BibTeX RDF	piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
1	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
1	Ted Stanion, Carl Sechen	Quasi-algebraic decompositions of switching functions.	ARVLSI	1995	DBLP DOI BibTeX RDF	quasi-algebraic decompositions, algebraic product, binary Boolean operation, canonical manner, SSL testable, logic testing, testability, switching functions, switching functions, state assignment, minimisation of switching nets, benchmark circuits, circuit size
1	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
1	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron

Publications at "ARVLSI"( http://dblp.L3S.de/Venues/ARVLSI )