Search results for "ASYNC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Mackenzie J. Wibbels, Baudouin Chauviere, Kenneth S. Stevens	Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer	ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné	A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Zhe Su, Hyunjung Hwang, Tristan Torchet, Giacomo Indiveri	Core Interface Optimization for Multi-core Neuromorphic Processors.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Cole Sherrill, Kyle Orman, Nicholas Brown, Jia Di	Case Study for Skewing MTNCL Circuits.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Xiang Wu, Rajit Manohar	Verification-Driven Design for Asynchronous VLSI.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Karthi Srinivasan, Yoram Moses, Rajit Manohar	Opportunistic Mutual Exclusion.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Jilin Zhang, Chunqi Qian, Dexuan Huo, Jian Zhang, Hong Chen 0002	Designing Self-timed Asynchronous Circuits with Chisel.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Prafull Purohit, Johannes Leugering, Rajit Manohar	An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Dexuan Huo, Jilin Zhang, Jian Zhang, Hong Chen 0002	A 28nm Energy-efficient Asynchronous SNN Accelerator with On-chip Learning for Gas Recognition.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Carsten Nielsen, Zhe Su, Giacomo Indiveri	Yak: An Asynchronous Bundled Data Pipeline Description Language.	ASYNC	2023	DBLP DOI BibTeX RDF
1		28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023	ASYNC	2023	DBLP DOI BibTeX RDF
1	Venkata Nori, Baudouin Chauviere, Mackenzie J. Wibbels, Kenneth S. Stevens	A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Ebelechukwu Esimai, Marly Roncken	Flexible Compilation and Refinement of Asynchronous Circuits.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Rajit Manohar, Yoram Moses	Timed Signalling Processes.	ASYNC	2023	DBLP DOI BibTeX RDF
1	Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet	An asynchronous hybrid pixel image sensor.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Jilin Zhang, Mingxuan Liang, Jinsong Wei, Shaojun Wei, Hong Chen	A 28nm Configurable Asynchronous SNN Accelerator with Energy-Efficient Learning.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Adrian Wheeldon, Alex Yakovlev, Rishad A. Shafik	Self-timed Reinforcement Learning using Tsetlin Machine.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam	Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Rui Li, Lincoln Berkley, Yihang Yang, Rajit Manohar	Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Alexander Kushnerov, Moti Medina, Alexandre Yakovlev	Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits.	ASYNC	2021	DBLP DOI BibTeX RDF
1		27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Beijing, China, September 7-10, 2021	ASYNC	2021	DBLP DOI BibTeX RDF
1	Spencer Nelson, Sang Yun Kim 0002, Jia Di, Zhe Zhou, Zhihang Yuan, Guangyu Sun 0003	Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Andrew Lines	Asynchronous Serial Infrastructure Using FPIO.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Prafull Purohit, Rajit Manohar	Hierarchical Token Rings for Address-Event Encoding.	ASYNC	2021	DBLP DOI BibTeX RDF
1	Matheus Trevisan Moreira, Stefano Giaconi	Chronos Link: A QDI Interconnect for Modern SoCs.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Felipe A. Kuentzer, Moisés Herrera, Oliver Schrape, Peter A. Beerel, Milos Krstic	Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Florian Huemer, Andreas Steininger	Timing Domain Crossing using Muller Pipelines.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory	Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Johannes Bund, Matthias Függer, Christoph Lenzen 0001, Moti Medina, Will Rosenbaum	PALS: Plesiochronous and Locally Synchronous Systems.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Lincoln S. Stevens, Mackenzie J. Wibbels, Valerie A. Wilkinson, Kenneth S. Stevens	Reducing Energy Consumption and Decentralizing Computing through Heat Redistribution.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Lindsay Kleeman	Recursive Formulations for N Input Asynchronous First Come First Served Arbiters.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet	A Self-Timed Ring based PUF.	ASYNC	2020	DBLP DOI BibTeX RDF
1		26th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2020, Salt Lake City, UT, USA, May 17-20, 2020	ASYNC	2020	DBLP BibTeX RDF
1	Justin Reiher, Mark R. Greenstreet	Optimization and Comparison of Synchronizers.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Victor Khomenko, Danil Sokolov, Alex Yakovlev, David Lloyd	Handshake Verification in WORKCRAFT.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Samira Ataei, Rajit Manohar	Shared-Staticizer for Area-Efficient Asynchronous Circuits.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias	Timing Errors in STA-based Gate-Level Simulation.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar	Cyclone: A Static Timing and Power Engine for Asynchronous Circuits.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Jennifer Paykin, Brian Huffman, Daniel M. Zimmerman, Peter A. Beerel	Formal Verification of Flow Equivalence in Desynchronized Designs.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans	A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Masashi Imai	Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices.	ASYNC	2020	DBLP DOI BibTeX RDF
1	Adrian Mardari, Zuzana Jelcicová, Jens Sparsø	Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Mickaël Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence	AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Ziyang Kang, Lei Wang 0011, Shasha Guo, Rui Gong, Yu Deng 0001, Qiang Dou	ASIE: An Asynchronous SNN Inference Engine for AER Events Processing.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland	A Hierarchical Approach to Self-Timed Circuit Verification.	ASYNC	2019	DBLP DOI BibTeX RDF
1		25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019	ASYNC	2019	DBLP BibTeX RDF
1	Mackenzie J. Wibbels, Shomit Das, Dheeraj Singh Takur, Venkata Nori, Kenneth S. Stevens	A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Alberto Moreno, Danil Sokolov, Jordi Cortadella	Synthesis from Waveform Transition Graphs.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Samira Ataei, Rajit Manohar	AMC: An Asynchronous Memory Compiler.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans	Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang	Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Jürgen Maier 0002, Matthias Függer, Thomas Nowak, Ulrich Schmid 0001	Transistor-Level Analysis of Dynamic Delay Models.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai	Hardware Trojan Insertion and Detection in Asynchronous Circuits.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Grégoire Gimenez, Jean Simatic, Laurent Fesquet	From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Yan Peng, Mark R. Greenstreet	Verifying Timed, Asynchronous Circuits using ACL2.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan	Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Rajit Manohar, Yoram Moses	Asynchronous Signalling Processes.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Jürgen Maier 0002, Andreas Steininger	Efficient Metastability Characterization for Schmitt-Triggers.	ASYNC	2019	DBLP DOI BibTeX RDF
1	Ghaith Tarawneh, Andrey Mokhov	Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Florian Huemer, Andreas Steininger	Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Shomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski	Case Study of Process Variation-Based Domain Partitioning of GPGPUs.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Oyinkuro Benafa, Danil Sokolov, Alex Yakovlev	Loadable Kessels Counter.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Justin Reiher, Mark R. Greenstreet, Ian W. Jones	Explaining Metastability in Real Synchronizers.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda	Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Sophie Germain, Sylvain Engels, Laurent Fesquet	A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies	Loihi Asynchronous Neuromorphic Research Chip.	ASYNC	2018	DBLP DOI BibTeX RDF
1		24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018	ASYNC	2018	DBLP BibTeX RDF
1	Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet	Static Timing Analysis of Asynchronous Bundled-Data Circuits.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Danil Sokolov, Victor Khomenko, Alex Yakovlev, David Lloyd	Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Yang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel	Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Sam Fok, Kwabena Boahen 0001	A Serial H-Tree Router for Two-Dimensional Arrays.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe	Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Matthias Függer, Attila Kinali, Christoph Lenzen 0001, Ben Wiederhake	Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland	Data-Loop-Free Self-Timed Circuit Verification.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Ning Qiao, Giacomo Indiveri	A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Alberto Moreno, Jordi Cortadella	State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Christoph Hoppe, Jens Döge, Peter Reichel, Patrick Russell, Andreas Reichel, Peter Schneider	A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data.	ASYNC	2018	DBLP DOI BibTeX RDF
1	Chun-Hong Shih, Jie-Hong R. Jiang	Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Montek Singh, Pintian Zhang, Andrew Vitkus, Ketan Mayer-Patel, Leandra Vicci	A Frameless Imaging Sensor with Asynchronous Pixels: An Architectural Evaluation.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Victor Khomenko, Danil Sokolov, Andrey Mokhov, Alex Yakovlev	WAITX: An Arbiter for Non-persistent Signals.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Alberto Moreno, Danil Sokolov, Alex Yakovlev, David Lloyd	Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Ameer M. S. Abdelhadi, Mark R. Greenstreet	Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Matthias Függer, Attila Kinali, Christoph Lenzen 0001, Thomas Polzer	Metastability-Aware Memory-Efficient Time-to-Digital Converters.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Weiwei Jiang 0002, Steven M. Nowick	A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Robert Najvirt, Thomas Polzer, Andreas Steininger	Measuring Metastability with Free-Running Clocks.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Alberto Moreno, Jordi Cortadella	Synthesis of All-Digital Delay Lines.	ASYNC	2017	DBLP DOI BibTeX RDF
1		23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017	ASYNC	2017	DBLP BibTeX RDF
1	Maxwell Waugaman, William Koven	Sharp - A Resilient Asynchronous Template.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Johnson Fernandes, Danil Sokolov, Alex Yakovlev	Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Rajit Manohar, Yoram Moses	The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Yang Zhang 0014, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel	Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet	A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi	Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda	MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Ghaith Tarawneh, Matthias Függer, Christoph Lenzen 0001	Metastability Tolerant Computing.	ASYNC	2017	DBLP DOI BibTeX RDF
1	Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun	Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.	ASYNC	2016	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca 0001, Sachin S. Sapatnekar	Ring Oscillator Clocks and Margins.	ASYNC	2016	DBLP DOI BibTeX RDF
1	Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside	Automatic Clock: A Promising Approach toward GALSification.	ASYNC	2016	DBLP DOI BibTeX RDF

Publications at "ASYNC"( http://dblp.L3S.de/Venues/ASYNC )