Search results for "EURO-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ayman M. Wahba, Dominique Borrione	Automatic diagnosis may replace simulation for correcting simple design errors.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Dirk Rabe, Wolfgang Nebel	New approach in gate-level glitch modelling.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Konrad Feyerabend, Rainer Schlör	Hardware synthesis from requirement specifications.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Bogdan G. Arsintescu, Sorin A. Spânoche	Global stacking for analog circuits.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Valentina Salapura, Volker Hamann	Implementing fuzzy control systems using VHDL and statecharts.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Rhodri M. Davies, John V. Woods	Timing verification for asynchronous design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Zeljko Mrcarica, Helmut Detter, Dejan Glozic, Vanco B. Litovski	Describing space-continuous models of microelectromechanical devices for behavioral simulation.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza, Luci Pirmez	Analysis of different protocol description styles in VHDL for high-level synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Eduardo de la Torre, J. Calvo, Javier Uceda	Model generation of test logic for macrocell based designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Gunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder	A VHDL reuse workbench.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Sabih H. Gerez, Erwin G. Woutersen	Assignment of storage values to sequential read-write memories.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Claus Schneider, Wolfgang Ecker	Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich	Incremental re-encoding for symbolic traversal of product machines.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Youn-Long Lin, Tsung-Yi Wu	Storage optimization by replacing some flip-flops with latches.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Vladimir B. Dmitriev-Zdorov	Generalized coupling as a way to improve the convergence in relaxation-based solvers.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Matthias A. Senn, Peter H. Schneider, Bernd Wurth	Power analysis for sequential circuits at logic level.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Michael Gschwind, Dietmar Maurer	An extendable MIPS-I processor kernel in VHDL for hardware/software co-design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Franz J. Rammig	Beyond VHDL: textual formalisms, visual techniques, or both?	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Ulrich Bretthauer, Ernst-Helmut Horneber	BRASIL: the Braunschweig mixed-mode-simulator for integrated circuits.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Christoph Grimm 0001, Klaus Waldschmidt	KIR - a graph-based model for description of mixed analog/digital systems.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara	A hierarchical approach to analog behavioral modeling of neural networks using HDL-A.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Georg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer	Hardware/software-cosimulation for mechatronic system design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Stefan Höreth	Compilation of optimized OBDD-algorithms.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Vladimir A. Shepelev, Stephen W. Director	Automatic workflow generation.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Markus Schwiegershausen, Holger Kropp, Peter Pirsch	A system level HW/SW partitioning and optimization tool.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	T. Murayama, Yuji Gendai	A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Francesco Curatelli, Marco Chirico, Leonardo Mangeruca	Specification and management of timing constraints in behavioral VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Andreas Hett, Bernd Becker 0001, Rolf Drechsler	MORE: an alternative implementation of BDD packages by multi-operand synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Kenneth Y. Yun	Automatic synthesis of extended burst-mode circuits using generalized C-elements.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Ekambaram Balaji, Prabhu Krishnamurthy	Modeling ASIC memories in VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Mitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki	A practical clock router that accounts for the capacitance derived from parallel and cross segments.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Yankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser	An approach for integrated specification and design of real-time systems.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Massoud Pedram, Jui-Ming Chang	Module assignment for low power.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Stefano Quer, Gianpiero Cabodi, Paolo Camurati	Decomposed symbolic forward traversals of large finite state machines.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi	A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Arno Kunzmann	Efficient random testing with global weights.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Jürgen Bortolazzi, Thomas Hirth, Thomas Raith	Specification and design of electronic control units.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Tobias H. Abthoff, Frank M. Johannes	TINA: analog placement using enumerative techniques capable of optimizing both area and net length.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Enrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	BDD-based testability estimation of VHDL designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Peter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín	A refinement calculus for VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo	Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	D. Gareth Evans, Peter N. Green, Derrick Morris	An integrated approach to engineering computer systems.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi	Entity overloading for mixed-signal abstraction in VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Wendell C. Baker, A. Richard Newton	The maximal VHDL subset with a cycle-level abstraction.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar	Testable path delay fault cover for sequential circuits.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser	A new concept for accurate modeling of VLSI interconnections and its application for timing simulation.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer 0002, Barry M. Pangrle, Rob Verbrugghe	A system for compiling and debugging structured data processing controllers.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo	Timing optimization by an improved redundancy addition and removal technique.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Graham Symonds, Wolfgang Nebel (eds.)	Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996	EURO-DAC	1996	DBLP BibTeX RDF
1	Peter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun	A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Giovanni De Micheli, Vincent John Mooney III, Claudionor Nunes Coelho, Toshiyuki Sakamoto	Synthesis from mixed specifications.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan	Component selection in resource shared and pipelined DSP applications.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski	Clock optimization for high-performance pipelined design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Rainer Leupers, Peter Marwedel	Instruction selection for embedded DSPs with complex instructions.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Michael J. Knieser, Christos A. Papachristou	COMET: a hardware-software codesign methodology.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Teresa Riesgo, Javier Uceda	A fault model for VHDL descriptions at the register transfer level.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Michael Ryba, Utz G. Baitinger	An integrated concept for design project planning and design flow control.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Mariagiovanna Sami, Anna Antola, Vincenzo Piuri	A high-level synthesis approach to optimum design of self-checking circuits.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Heinz-Josef Eikerling, Wolfgang Rosenstiel	Automatic structuring and optimization of hierarchical designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Guido Schumacher, Wolfgang Nebel	Object-oriented hardware modelling - where to apply and what are the objects?	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Stephanus Büttgenbach	Spotlights on recent developments in microsystem technology.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Christian Veith, Klaus Buchenrieder, Andreas Pyttel	Mapping statechart models onto an FPGA-based ASIP architecture.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Krzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski	Synchronous parallel controller synthesis from behavioural multiple-process VHDL description.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Sanjiv Narayan, Daniel D. Gajski	Rapid performance estimation for system design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Karl van Rompaey, Ivo Bolsens, Hugo De Man, Diederik Verkest	CoWare - a design environment for heterogenous hardware/software systems.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Adel Changuel, Ahmed Amine Jerraya, Robin Rolland	Design of an adaptive motors controller based on fuzzy logic using behavioral synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	J. Bullmann, Wolfgang Rosenstiel, Endric Schubert, Udo Kebschull	Library based technology mapping using multiple domain representations.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Wolfgang Süß, Horst Eggert, Martina Gorges-Schleuter, Wilfried Jakob, S. Meinzer, Alexander Quinte	Simulation and design optimization of microsystems based on standard simulators and adaptive search techniques.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Takashi Mitsuhashi, Masami Murakata, Kenji Yoshida, Takahiro Aoki	Physical design CAD in deep sub-micron era.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Andrew Crews, Forrest Brewer	Controller optimization for protocol intensive applications.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Klaus D. Müller-Glaser	CAD of microsystems - a challenge for system engineering.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Ivan Hom, John J. Granacki	Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Manfred Koegst, Klaus Feske, Günter Franke	State assignment for FSM low power design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Ambar Sarkar	System design using an integrated specification and performance modeling methodology.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Kevin O'Brien, Serge Maginot, Anne Robert	Towards maximising the use of structural VHDL for synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Mohamed Abid, Adel Changuel, Ahmed Amine Jerraya	Exploration of hardware/software design space through a codesign of robot arm controller.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Ernst Christen, Kenneth Bakalar	VHDL 1076.1 - analog and mixed signal extensions to VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Armin Bender	MILP based task mapping for heterogeneous multiprocessor systems.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Christos A. Papachristou, Mehrdad Nourani	False path exclusion in delay analysis of RTL-based datapath-controller designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Claus Mayer, Jörg Pleickhardt, Hans Sahm	A graphical data management system for HDL-based ASIC design projects.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Vinoo Srinivasan, Nand Kumar, Ranga Vemuri	Hierarchical behavioral partitioning for multicomponent synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli	Hardware/software partitioning of VHDL system specifications.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Henrik Esbensen, Ernest S. Kuh	EXPLORER: an interactive floorplanner for design space exploration.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Donatella Sciuto, Luciano Baresi, Cristiana Bolchini	Software methodologies for VHDL code static analysis based on flow graphs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	M. Robson, G. Russell	A digital method for testing embedded switched capacitor filters.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda	Fault tolerant and BIST design of a FIFO cell.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	João Paulo Teixeira 0001, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos	VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
1	Theodore Karoubalis, George Alexiou, Nick Kanopoulos	Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Serafín Olcoz, Luis Entrena, Luis Berrojo	An effective system development environment based on VHDL prototyping.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	D. Galán, Carlos Jesús Jiménez-Fernández, Angel Barriga, Santiago Sánchez-Solano	VHDL package for description of fuzzy logic controllers.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Eugen Röhm	Latest benchmark results of VHDL simulation systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Enrico Macii, Massimo Poncino	Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Smita Bakshi, Daniel D. Gajski	A memory selection algorithm for high-performance pipelines.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Franco Fummi, U. Rovati, Donatella Sciuto	Testable synthesis of high complex control devices.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Laurent Arditi, Hélène Collavizza	Towards verifying VHDL descriptions of processors.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Zahir Moosa, Nick Filer, Michael Brown, J. Heaton, J. Pye	Practical inter-operation of CAD tools using a flexible procedural interface.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins	Performance-oriented placement and routing for field-programmable gate arrays.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Mahsa Vahidi, Alex Orailoglu	Metric-based transformations for self testable VLSI designs with high test concurrency.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ulrike Ober, Manfred Glesner	Multiway netlist partitioning onto FPGA-based board architecture.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ulrich Weinmann, Oliver Bringmann 0001, Wolfgang Rosenstiel	Device selection for system partitioning.	EURO-DAC	1995	DBLP DOI BibTeX RDF

Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )