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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 3186 publication records. Showing 3186 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Mohammadmahdi Mazraeli, Yu Gao, Paul Chow |
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center.  |
FPL  |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukas Stasytis, Zsolt István |
Optimization Techniques for Hestenes-Jacobi SVD on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Haishuang Fan, Jingya Wu, Wenyan Lu, Xiaowei Li 0001, Guihai Yan |
Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Shashwat Khandelwal, Shanker Shreejith |
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing |
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | José Oliver 0002, Carlos Álvarez 0001, Teresa Cervero, Xavier Martorell, John D. Davis, Eduard Ayguadé |
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes |
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Felix Jentzsch |
Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuqi Zhu, Cong Gao, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier |
Bayesian Optimization for Efficient Heterogeneous MPSoC Based DNN Accelerator Runtime Tuning. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruichen Chen, Shengyao Lu, Mohamed A. Elgammal, Peter Chun, Vaughn Betz, Di Niu |
VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Baoze Zhao, Wenjin Huang, Yihua Huang 0005 |
A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews 0001, Miaoqing Huang |
Accelerating LSTM-Based High-Rate Dynamic System Models. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuntao Han, Qiang Liu |
HPTA: A High Performance Transformer Accelerator Based on FPGA. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Myrtle Shah, Jakob Ternes, Dirk Koch |
FABulous Demo: Open Source FPGA on Sky130. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Huimin Li 0004, Phillip Rieger, Shaza Zeitouni, Stjepan Picek, Ahmad-Reza Sadeghi |
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Louis Ledoux, Marc Casas |
An Open-Source Framework for Efficient Numerically-Tailored Computations. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Offel, Andreas Ley, Sven Hager |
HashCache: High-Performance State Tracking for Resilient FPGA-Based Packet Processing. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Changjun Song, Yongming Tang, Jiyuan Liu 0006, Sige Bian, Danni Deng, He Li 0008 |
MSDF-SGD: Most-Significant Digit-First Stochastic Gradient Descent for Arbitrary-Precision Training. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Abi-Karam, Cong Hao |
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhenya Zang, Uwe Dolinsky, Pietro Ghiglio, Stefano Cherubin, Mehdi Goli 0001, Shufan Yang |
Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seungwon Min, Wen-Mei W. Hwu, Deming Chen |
FSSD: FPGA-Based Emulator for SSDs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Joshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas, William B. Toms, Mikel Luján, John Goodacre |
DiAD - Distributed Acceleration for Datacenter FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Yueyin Bai, Hao Zhou 0008, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu 0010, Kun Wang 0005 |
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhav Kashera, Siddhant Jain, Abhishek Banerjee, Suresh Purini |
Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaorang Guo, Martin Schulz 0001 |
A Scalable and Cross-Technology Quantum Control Processor. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson |
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna |
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001 |
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Kimia Talaei Khoozani, Arash Ahmadian Dehkordi, Vaughn Betz |
Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Hahn, Stefan Wildermann, Jürgen Teich |
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ziyi Yang, Suhaib A. Fahmy |
Exploring FPGA Acceleration for Distributed Serverless Computing. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Liu, Xiaoming He, Jun Yu, Kun Wang |
DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang 0001 |
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolai Müller, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori, Amir Moradi 0001 |
Automated Masking of FPGA-Mapped Designs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Hanning Chen, Ali Zakeri, Fei Wen, Hamza Errahmouni Barkam, Mohsen Imani |
HyperGRAF: Hyperdimensional Graph-Based Reasoning Acceleration on FPGA. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabriel Rodriguez-Canal, Nick Brown 0002, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus |
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede |
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Yang 0111, Weihang Long, Rajgopal Kannan, Viktor K. Prasanna |
FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data Layout. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk |
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiqi Chen, Haoyang Zhang, Shun Li, Enhao Tang, Jun Yu 0010, Kun Wang 0005 |
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Boutros, Stephen More, Vaughn Betz |
A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices? |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Yunyi Zhao, Yunjia Xia, Rui C. V. Loureiro, Hubin Zhao, Uwe Dolinsky, Shufan Yang |
FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhewen Yu, Christos-Savvas Bouganis |
Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Rémi Garcia 0002, Anastasia Volkova |
Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer |
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Nele Mentens, Leonel Sousa, Pedro Trancoso, Nikela Papadopoulou, Ioannis Sourdis (eds.) |
33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023 |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Rubén Macias, Sergio Bernabé, Carlos González |
Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp Kreowsky, Justin Knapheide, Benno Stabernack |
Challenges Using FPGA Clusters for Distributed CNN Training. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Petros Toupas, Christos-Savvas Bouganis, Dimitrios Tzovaras |
fpgaHART: A Toolflow for Throughput-Oriented Acceleration of 3D CNNs for HAR onto FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Langhammer, George A. Constantinides |
eGPU: A 750 MHz Class Soft GPGPU for FPGA. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Krautter, Paul R. Genssler, Gloria Sepanta, Hussam Amrouch, Mehdi B. Tahoori |
Stress-Resiliency of AI Implementations on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiqing Li, Shien Zhu, Xiangzhong Luo, Tao Luo, Weichen Liu |
An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Hans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi |
Towards Coarse-Grained Reconfigurable Approximate Computing with CGRAgen. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek |
SPADES: A Productive Design Flow for Versal Programmable Logic. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Amin Mohaghegh, Vaughn Betz |
Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang 0005, Lei He 0001 |
Token Packing for Transformers with Variable-Length Inputs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaden M. Alismail, Dirk Koch |
Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Justin Knapheide, Philipp Kreowsky, Benno Stabernack |
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph Niemann 0002, Michael Rethfeldt, Dirk Timmermann |
A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Veronia Iskandar, Mohamed A. Abd El Ghany, Diana Goehringer |
Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Vincent Meyers, Michael Hefenbrock, Dennis Gnad, Mehdi Baradaran Tahoori |
Remote Identification of Neural Network FPGA Accelerators by Power Fingerprints. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis Sourdis, Nele Mentens, Leonel Sousa, Pedro Trancoso |
Preface. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis |
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders |
Improving the Reliability of FPGA CRO PUFs. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiqi Chen, Haoyang Zhang, Jun Yu 0010, Kun Wang 0005 |
FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors. |
FPL |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen Wu, Zhuofu Tao, Kun Wang 0005, Lei He 0001 |
SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Anqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan 0002, Yingyan Lin, Ang Li 0006, Martin C. Herbordt |
A Framework for Neural Network Inference on FPGA-Centric SmartNICs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon |
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz |
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Sahand Kashani, Mahyar Emami, James R. Larus |
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis R. E. Gnad, Jiaqi Hu, Mehdi B. Tahoori |
Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault Attacks. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Hong Wang, Rongzhang Zheng, Satyaprakash Pareek, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan |
XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Marie Auffret, Erwei Wang, James J. Davis 0001 |
FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Chan-Wei Hu, Jiang Hu, Sunil P. Khatri |
TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Yingxue Gao, Lei Gong, Chao Wang 0003, Teng Wang, Xuehai Zhou |
SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides |
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang 0005, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang |
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Zelin Wang, Ke Zhang 0017, Yisong Chang, Yanlong Yin, Yuxiao Chen 0009, Ran Zhao, Songyue Wang, Mingyu Chen 0001, Yungang Bao |
FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk |
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolai Fiege, Patrick Sittel, Peter Zipf |
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Trautmann 0001, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann |
Real-Time Waveform Matching with a Digitizer at 10 GS/s. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Böttcher, Martin Kumm, Florent de Dinechin |
Resource Optimal Squarers for FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Yashael Faith Arthanto, David Ojika, Joo-Young Kim 0001 |
FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Liu, Sunrui Zhang, Xiaole Cui |
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Bardia Babaei, Dirk Koch |
Tunable Fine-grained Clock Phase-shifting for FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Montgomerie-Corcoran, Zhewen Yu, Christos-Savvas Bouganis |
SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Cornelia Wulf, Najdet Charaf, Diana Göhringer |
Virtualization of Reconfigurable Mixed-Criticality Systems. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Martha Barker, Stephen A. Edwards, Martha A. Kim |
Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolai Fiege, Patrick Sittel, Peter Zipf |
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Argyris Kokkinis, Dionysios Diamantopoulos, Kostas Siozios |
Dynamic Heap Management in High-Level Synthesis for Many-Accelerator Architectures. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Myrtle Shah |
FPL Demo: Hot Reconfiguration - Partial Reconfiguration without Bounds. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Cecilia Latotzke, Tim Ciesielski, Tobias Gemmeke |
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph Powell, Kaspar Matas, Kristiyan Manev, Dirk Koch |
FPL Demo: FPGA Bitstream Virus Scanning. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ziying Ni, Ayesha Khalid, Máire O'Neill |
High Performance FPGA-based Post Quantum Cryptography Implementations. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Kamaleldin, Diana Göhringer |
A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich |
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Ariel Podlubne, Johannes Mey, Sergio A. Pertuz 0001, Uwe Aßmann, Diana Göhringer |
Model-based Generation of Hardware/Software Architectures for Robotics Systems. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Peng Zhang, Shijun Zhang, Shang Li, Jin Zhang, Shaoxun Liu, Youjun Bu |
FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Seongyoung Kang, Tarun Sai Ganesh Nerella, Shashank Uppoor, Sang-Woo Jun |
BunchBloomer: Cost-Effective Bloom Filter Accelerator for Genomics Applications. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Yee Yang Tan, Felix Staudigl, Lukas Jünger 0001, Anna Drewes, Rainer Leupers, Jan Moritz Joseph |
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
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