Search results for "HiPEAC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Samer Arandi, Paraskevas Evripidou	DDM-VMc: the data-driven multithreading virtual machine for the cell processor.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Shisheng Li, Buqi Cheng, Xiao-Feng Li	TypeCastor: demystify dynamic typing of JavaScript applications.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Manolis Katevenis, Margaret Martonosi, Christos Kozyrakis, Olivier Temam (eds.)	High Performance Embedded Architectures and Compilers, 6th International Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26, 2011. Proceedings	HiPEAC	2011	DBLP BibTeX RDF
1	Kristof Du Bois, Tim Schaeps, Stijn Polfliet, Frederick Ryckbosch, Lieven Eeckhout	SWEEP: evaluating computer system energy efficiency using synthetic workloads.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Ahmed Abousamra, Alex K. Jones, Rami G. Melhem	NoC-aware cache design for multithreaded execution on tiled chip multiprocessors.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Mario Kicherer, Rainer Buchty, Wolfgang Karl	Cost-aware function migration in heterogeneous systems.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Matthew DeVuyst, Dean M. Tullsen, Seon Wook Kim	Runtime parallelization of legacy code on a transactional memory system.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Marcus Edvinsson, Jonas Lundberg, Welf Löwe	Parallel points-to analysis for multi-core machines.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Souvik Bhattacherjee, Ankur Narang, Vikas K. Garg	High throughput data redundancy removal algorithm with scalable performance.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Pierre Michaud	Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	David Eklov, David Black-Schaffer, Erik Hagersten	Fast modeling of shared caches in multicore systems.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas	GLOpenCL: OpenCL support on hardware- and software-managed cache multicores.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	R. Manikantan, R. Govindarajan, Kaushik Rajan	Extended histories: improving regularity and performance in correlation prefetchers.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Jaume Abella 0001, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero	RVC: a mechanism for time-analyzable real-time processors with faulty caches.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Dominik Grewe, Zheng Wang 0001, Michael F. P. O'Boyle	A workload-aware mapping approach for data-parallel programs.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Antonio González 0001	Moore's law implications on energy reduction.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Saman P. Amarasinghe	PetaBricks: a language and compiler based on autotuning.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Antoniu Pop, Albert Cohen 0001	A stream-computing extension to OpenMP.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Faizur Rahman, Jichi Guo, Qing Yi	Automated empirical tuning of scientific codes for performance and power consumption.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Julien Dusser, André Seznec	Decoupled zero-compressed memory.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Jason Mars, Lingjia Tang, Mary Lou Soffa	Directly characterizing cross core interference through contention synthesis.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Erven Rohou, Sergei Dyshel, Dorit Nuzman, Ira Rosen, Kevin Williams 0001, Albert Cohen 0001, Ayal Zaks	Speculatively vectorized bytecode.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil D. Dutt	RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny	Performance and Power Aware CMP Thread Allocation Modeling.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Boubacar Diouf, Albert Cohen 0001, Fabrice Rastello, John Cavazos	Split Register Allocation: Linear Complexity Without the Performance Penalty.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Shekhar Srikantaiah, Mahmut T. Kandemir	SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Magnus Jahre, Marius Grannæs, Lasse Natvig	DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Roger Espasa	Larrabee: A Many-Core Intel Architecture for Visual Computing.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf	An Application-Aware Load Balancing Strategy for Network Processors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke	Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Frédéric de Mesmay, Srinivas Chellappa, Franz Franchetti, Markus Püschel	Computer Generation of Efficient Software Viterbi Decoders.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy	Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yuejian Xie, Gabriel H. Loh	Scalable Shared-Cache Management by Containing Thrashing Workloads.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Olga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn	Trace-Based Data Layout Optimizations for Multi-core Processors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Roger Ferrer, Vicenç Beltran 0001, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Analysis of Task Offloading for Accelerators.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	George Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios S. Nikolopoulos, Angelos Bilas	Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras	Accelerating XML Query Matching through Custom Stack Generation on FPGAs.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Bob Iannucci	Embedded Systems as Datacenters.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Pete Cooper, Uwe Dolinsky, Alastair F. Donaldson, Andrew Richards, Colin Riley, George Russell	Offload - Automating Code Migration to Heterogeneous Multicore Systems.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Henry Hoffmann, David Wentzlaff, Anant Agarwal	Remote Store Programming.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Alexander Monakov, Anton Lokhmotov, Arutyun Avetisyan	Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Yunheung Paek	Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne	Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yunlian Jiang, Kai Tian, Xipeng Shen	Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	John Sartori, Rakesh Kumar 0002	Low-Overhead, High-Speed Multi-core Barrier Synchronization.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell (eds.)	High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris C. Kirkham, Ian Watson	Improving Performance by Reducing Aborts in Hardware Transactional Memory.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Maik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet	Mapping and Synchronizing Streaming Applications on Cell Processors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Frederik Vandeputte, Lieven Eeckhout	Finding Stress Patterns in Microprocessor Workloads.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne	MPSoC Design Using Application-Specific Architecturally Visible Communication.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Sai Prashanth Muralidhara, Mahmut T. Kandemir	Communication Based Proactive Link Power Management.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Hassan A. Salamy, J. Ramanujam	A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan	Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Ghiath Al-Kadi, Andrei Sergeevich Terechko	A Hardware Task Scheduler for Embedded Video Processing.	HiPEAC	2009	DBLP DOI BibTeX RDF	Hardware task scheduler, task dependency patterns, H.264 video compression, embedded video processing
1	Michael B. Henry, Leyla Nazhandali	Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Major Bhadauria, Vincent M. Weaver, Sally A. McKee	Accomodating Diversity in CMPs with Heterogeneous Frequencies.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly	Deriving Efficient Data Movement from Decoupled Access/Execute Specifications.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Grigori Fursin, Olivier Temam	Collective Optimization.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Tilak Agerwala	Keynote: Challenges on the Road to Exascale Computing.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	François Bodin	Keynote: Compilers in the Manycore Era.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Mattias V. Eriksson, Christoph W. Kessler	Integrated Modulo Scheduling for Clustered VLIW Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Martin Thuresson, Magnus Själander, Per Stenström	A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer (eds.)	High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke	Revisiting Cache Block Superloading.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho	Parallel LDPC Decoding on the Cell/B.E. Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan	In-Network Caching for Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro	Predictive Runtime Code Scheduling for Heterogeneous Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Mohammed Fellahi, Albert Cohen 0001	Software Pipelining in Nested Loops with Prolog-Epilog Merging.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout	MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez 0001, Alex Ramírez	Parallel H.264 Decoding on an Embedded Multicore Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Omer Khan, Sandip Kundu	Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.	HiPEAC	2009	DBLP DOI BibTeX RDF	Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS)
1	Daniel Jones 0005, Nigel P. Topham	High Speed CPU Simulation Using LTU Dynamic Binary Translation.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Muhammad Umar Farooq 0003, Lizy Kurian John, Margarida F. Jacome	Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF	Tiled dataflow architectures, predication, power-performance trade-offs
1	Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson	Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer	IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González	Drug Design Issues on the Cell BE.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere	Experiences with Parallelizing a Bio-informatics Program on the Cell BE.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Chun-Chieh Lin, Chuen-Liang Chen	Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory.	HiPEAC	2008	DBLP DOI BibTeX RDF	embedded system, memory management, interpreter, Java virtual machine, power-saving, NAND flash memory, cache miss, code placement
1	Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev	Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Stijn Eyerman, Lieven Eeckhout, James E. Smith 0001	Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Patrick Akl, Andreas Moshovos	Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero	LPA: A First Approach to the Loop Processor Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU Cache Power Management in Multiple Clock Domain Processors.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Subhradyuti Sarkar, Dean M. Tullsen	Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	BRAM-LUT Tradeoff on a Polymorphic DES Design.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal	Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Mateo Valero, Jesús Labarta	Supercomputing for the Future, Supercomputing from the Past (Keynote).	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Vincent M. Weaver, Sally A. McKee	Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest	Coffee: COmpiler Framework for Energy-Aware Exploration.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	James Psota, Anant Agarwal	rMPI: Message Passing on Multicore Processors with On-Chip Interconnect.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
1	Kevin D. Kissell	MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Tzi-cker Chiueh	Fast Bounds Checking Using Debug Register.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Per Stenström, Michel Dubois 0001, Manolis Katevenis, Rajiv Gupta 0001, Theo Ungerer (eds.)	High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen	Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.	HiPEAC	2008	DBLP DOI BibTeX RDF

Publications at "HiPEAC"( http://dblp.L3S.de/Venues/HiPEAC )