|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
No Growbag Graphs found.
|
|
|
Results
Found 24 publication records. Showing 24 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Ahmed Hemani, Juha Plosila, Giovanni Beltrame, Hannu Tenhunen |
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh |
A GALS Router for Asynchronous Network-on-Chip. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti 0001 |
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Masoud Daneshtalab, Masoumeh Ebrahimi, Maurizio Palesi, Federico Angiolini, Juha Plosila (eds.) |
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, MES'2014, in conjunction with the 41st International Symposium on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15, 2014. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christian Pinto, Andrea Marongiu, Luca Benini |
A Virtualization Framework for IOMMU-less Many-Core Accelerators. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ehsan Atoofian |
Acceleration of Software Transactional Memory through Hardware Clock. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ismail Akturk, Özcan Özturk 0001 |
Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Xuhao Chen 0001, Shengzhao Wu, Li-Wen Chang, Wei-Sheng Huang, Carl Pearson, Zhiying Wang 0003, Wen-mei W. Hwu |
Adaptive Cache Bypass and Insertion for Many-core Accelerators. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Davide Patti |
A Low-resource and Scalable Strategy for Segment Partitioning of Many-core Nano Networks. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono |
A Closed Loop Control based Power Manager for WiNoC Architectures. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | David Watson, Ali Ahmadinia, Gordon Morison, Tom Buggy |
Hardware Threading Techniques for Multi-Threaded MPSoCs. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hayder Al-Khalissi, Mladen Berekovic, Andrea Marongiu |
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores. |
MES |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini |
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Shuo Li 0002, Jamshaid Sarwar Malik, Shaoteng Liu, Ahmed Hemani |
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Satoshi Kawakami, Akihito Iwanaga, Koji Inoue |
Many-core acceleration for model predictive control systems. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Sandro Bartolini, Paolo Grani |
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou |
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini |
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Vijayalakshmi Saravanan, S. Kaushik, P. Sai Krishna, Dwarkadas Pralhaddas Kothari |
Performance analysis of multi-threaded multi-core CPUs. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Masoud Daneshtalab, Ahmed Hemani, Maurizio Palesi (eds.) |
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Akio Shimada, Balazs Gerofi, Atsushi Hori, Yutaka Ishikawa |
Proposing a new task model towards many-core architecture. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Mamata Dalui, Keshav Gupta, Biplab K. Sikdar |
Directory based cache coherence verification logic in CMPs cache system. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Manuel Selva, Lionel Morel, Kevin Marquet, Stéphane Frénot |
Extending dataflow programs with throughput properties. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Ben Kelly, William B. Gardner, Shorin Kyo |
AutoPilot: message passing parallel programming for a cache incoherent embedded manycore processor. |
MES |
2013 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #24 of 24 (100 per page; Change: )
|
|