Search results for "MTDT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Charles Hsu	Future Prospective of Programmable Logic Non-volatile Device.	MTDT	2006	DBLP DOI BibTeX RDF
1		Organizing Committee.	MTDT	2006	DBLP DOI BibTeX RDF
1	Hsing-Chung Liang, Le-Quen Tzeng	Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories.	MTDT	2006	DBLP DOI BibTeX RDF
1	Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa	MRAM Write Error Categorization with QCKB.	MTDT	2006	DBLP DOI BibTeX RDF
1		Foreword.	MTDT	2006	DBLP DOI BibTeX RDF
1	Peter Muhmenthaler	New on-Chip DFT and ATE Features for Efficient Embedded Memory Test.	MTDT	2006	DBLP DOI BibTeX RDF
1	T. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian	A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults.	MTDT	2006	DBLP DOI BibTeX RDF
1	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
1	Victor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun	Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory.	MTDT	2006	DBLP DOI BibTeX RDF
1		Program Committee.	MTDT	2006	DBLP DOI BibTeX RDF
1	Chih-Yuan Lu	Non-volatile Semiconductor Memory Technology in Nanotech Era.	MTDT	2006	DBLP DOI BibTeX RDF
1	Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev	Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.	MTDT	2006	DBLP DOI BibTeX RDF
1	Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou	SRAM Cell Current in Low Leakage Design.	MTDT	2006	DBLP DOI BibTeX RDF
1	Pei-Lin Pai	DRAM Industry Trend.	MTDT	2006	DBLP DOI BibTeX RDF
1	Jia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao	Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash Memory.	MTDT	2006	DBLP DOI BibTeX RDF
1	Mohamed Azimane	High-Quality Memory Test.	MTDT	2006	DBLP DOI BibTeX RDF
1	Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene	On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.	MTDT	2006	DBLP DOI BibTeX RDF
1	Riichiro Shirota	Roadmap of the Flash Memory.	MTDT	2006	DBLP DOI BibTeX RDF
1	Jyi-Tsong Lin, Mike Chang	A New 1T DRAM Cell With Enhanced Floating Body Ef.	MTDT	2006	DBLP DOI BibTeX RDF
1	Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng	Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.	MTDT	2006	DBLP DOI BibTeX RDF
1	Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu	Fault-Pattern Oriented Defect Diagnosis for Flash Memory.	MTDT	2006	DBLP DOI BibTeX RDF
1	Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson	DDR2 DRAM Output Timing Optimization.	MTDT	2006	DBLP DOI BibTeX RDF
1	Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu	FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.	MTDT	2006	DBLP DOI BibTeX RDF
1		14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan	MTDT	2006	DBLP BibTeX RDF
1		Reviewers.	MTDT	2006	DBLP DOI BibTeX RDF
1	Ching-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin, Charles Ching-Hsiang Hsu	Embedded OTP fuse in CMOS logic process.	MTDT	2005	DBLP DOI BibTeX RDF
1		13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan	MTDT	2005	DBLP BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth	Impact of stresses on the fault coverage of memory tests.	MTDT	2005	DBLP DOI BibTeX RDF
1	Yang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming-Hsueh Chuang, Jheng-Yao Lin	DFT architecture for a dynamic fault model of the embedded mask ROM of SOC.	MTDT	2005	DBLP DOI BibTeX RDF
1	Chin-Long Wey, Meng-Yao Liu, Shaolei Quan	Reliability enhancement of CMOS SRAMs.	MTDT	2005	DBLP DOI BibTeX RDF
1	Matthew J. Breitwisch, Chung Hon Lam, Jeffrey B. Johnson, Steven W. Mittl, Jian W. Zhu	A novel CMOS compatible embedded nonvolatile memory with zero process adder.	MTDT	2005	DBLP DOI BibTeX RDF
1	Kamlesh R. Raiter, Bruce F. Cockburn	An investigation into three-level ferroelectric memory.	MTDT	2005	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang	A BIRA algorithm for embedded memories with 2D redundancy.	MTDT	2005	DBLP DOI BibTeX RDF
1	Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang	FSM-based programmable memory BIST with macro command.	MTDT	2005	DBLP DOI BibTeX RDF
1	Valerie Lines, Robert McKenzie, Hakjune Oh, Hong-Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin-Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric C. Jones, Matthew Silverstein	A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability.	MTDT	2005	DBLP DOI BibTeX RDF
1	Meng-Yi Wu, Shin-Chang Feng, Ya-Chin King	A novel single poly-silicon EEPROM using trench floating gate.	MTDT	2005	DBLP DOI BibTeX RDF
1	Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang	Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM.	MTDT	2005	DBLP DOI BibTeX RDF
1	Bruce McGaughy, S. Wünsche, K. K. Hung	Advanced simulation technology and its application in memory design and verification.	MTDT	2005	DBLP DOI BibTeX RDF
1	Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai	Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique.	MTDT	2005	DBLP DOI BibTeX RDF
1	Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama	DFT techniques for memory macro with built-in ECC.	MTDT	2005	DBLP DOI BibTeX RDF
1	Serguei Okhonin, Pierre Fazan, Mark-Eric Jones	Zero capacitor embedded memory technology for system on chip.	MTDT	2005	DBLP DOI BibTeX RDF
1	Jin-Fu Li 0001, Yu-Jane Huang	An error detection and correction scheme for RAMs with partial-write function.	MTDT	2005	DBLP DOI BibTeX RDF
1	Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen	A systematic approach to reducing semiconductor memory test time in mass production.	MTDT	2005	DBLP DOI BibTeX RDF
1	Simon C. Li, J. P. Su, T.-H. Wu, J. M. Lee, M. F. Shu	Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applications.	MTDT	2005	DBLP DOI BibTeX RDF
1	Amandeep Singh, Debashish Bose, Sandeep Darisala	Software based in-system memory test for highly available systems.	MTDT	2005	DBLP DOI BibTeX RDF
1	Ching-Hua Hsiao, Ding-Ming Kwai	Measurement and characterization of 6T SRAM cell current.	MTDT	2005	DBLP DOI BibTeX RDF
1	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	A programmable built-in self-test for embedded DRAMs.	MTDT	2005	DBLP DOI BibTeX RDF
1	Shin-Pao Cheng, Shi-Yu Huang	A low-power SRAM design using quiet-bitline architecture.	MTDT	2005	DBLP DOI BibTeX RDF
1	Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King	Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory.	MTDT	2005	DBLP DOI BibTeX RDF
1	Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee	A high speed BIST architecture for DDR-SDRAM testing.	MTDT	2005	DBLP DOI BibTeX RDF
1	Star Sung, Thomas Chang, Juei Lung Chen	A nor-type MLC ROM with novel sensing scheme for embedded applications.	MTDT	2005	DBLP DOI BibTeX RDF
1	Wei-Lun Wang, Kuen-Jong Lee	A complete memory address generator for scan based March algorithms.	MTDT	2005	DBLP DOI BibTeX RDF
1	Xiaogang Du, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Sudhakar M. Reddy	Full-speed field programmable memory BIST supporting multi-level looping.	MTDT	2005	DBLP DOI BibTeX RDF
1	Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor	The State-of-Art and Future Trends in Testing Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
1	Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars	The Effectiveness of the Scan Test and Its New Variants.	MTDT	2004	DBLP DOI BibTeX RDF
1		12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA	MTDT	2004	DBLP BibTeX RDF
1	Luca Schiano, Marco Ottavi, Fabrizio Lombardi	Markov Models of Fault-Tolerant Memory Systems under SEU.	MTDT	2004	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Shih-Chang Huang	Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.	MTDT	2004	DBLP DOI BibTeX RDF
1	Bruce F. Cockburn	Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory.	MTDT	2004	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor	Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.	MTDT	2004	DBLP DOI BibTeX RDF	Bit line twisting, bit line coupling, DRAMs, crosstalk noise, defect simulation, faulty behavior
1	R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald	An Integrated Memory Self Test and EDA Solution.	MTDT	2004	DBLP DOI BibTeX RDF
1	Robert C. Aitken	Redundancy & It's Not Just for Defects Anymore.	MTDT	2004	DBLP DOI BibTeX RDF
1	Jaafar Alghazo, Adil Akaaboune, Nazeih Botros	SF-LRU Cache Replacement Algorithm.	MTDT	2004	DBLP DOI BibTeX RDF	LFU, Replacement, LRU, Low Power Cache
1	Elaine Ou, Woodward Yang	Fast Error-Correcting Circuits for Fault-Tolerant Memory.	MTDT	2004	DBLP DOI BibTeX RDF
1	Swapnil Bahl	A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared Controller.	MTDT	2004	DBLP DOI BibTeX RDF
1	Michael Spica, T. M. Mak	Do We Need Anything More Than Single Bit Error Correction (ECC)?	MTDT	2004	DBLP DOI BibTeX RDF
1	Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu	A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
1	Saman Adham, Benoit Nadeau-Dostie	A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF
1	N. Derhacobian, Valery A. Vardanian, Yervant Zorian	Embedded Memory Reliability: The SER Challenge.	MTDT	2004	DBLP DOI BibTeX RDF
1	Adil Akaaboune, Nazeih Botros, Jaafar Alghazo	Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design.	MTDT	2004	DBLP DOI BibTeX RDF	Tag-Skipping, Victim Cache, Low-Power Cache
1	Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani	A Programmable Built-in Self-Diagnosis for Embedded SRAM.	MTDT	2004	DBLP DOI BibTeX RDF
1	Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani	Micro Programmable Built-In Self Repair for SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor	A Fault Primitive Based Analysis of Linked Faults in RAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Memory testing, march tests, functional fault models, linked faults, fault primitives
1	Betty Prince	Application Specific DRAMs Today.	MTDT	2003	DBLP DOI BibTeX RDF
1	Robert C. Aitken	Applying Defect-Based Test to Embedded Memories in a COT Model.	MTDT	2003	DBLP DOI BibTeX RDF
1	Roger Barth	ITRS Commodity Memory Roadmap.	MTDT	2003	DBLP DOI BibTeX RDF
1	Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott	A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.	MTDT	2003	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Ad J. van de Goor	Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes.	MTDT	2003	DBLP DOI BibTeX RDF	two floating nodes, memory testing, DRAMs, dynamic faults, defect simulation
1	Baosheng Wang, Josh Yang, André Ivanov	Reducing Test Time of Embedded SRAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time
1	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
1		11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA	MTDT	2003	DBLP BibTeX RDF
1	Youhei Zenda, Koji Nakamae, Hiromu Fujioka	Cost Optimum Embedded DRAM Design by Yield Analysis.	MTDT	2003	DBLP DOI BibTeX RDF
1	Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001	A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.	MTDT	2003	DBLP DOI BibTeX RDF
1	Daniel Salamon, Bruce F. Cockburn	An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell.	MTDT	2003	DBLP DOI BibTeX RDF
1	Jean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua	A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications.	MTDT	2003	DBLP DOI BibTeX RDF
1	Jörg E. Vollrath	Output Timing Measurement Using an Idd Method.	MTDT	2003	DBLP DOI BibTeX RDF	DDR, timing, DRAM
1	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, Cecilia Metra, Bruno Riccò	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	Caroline Papaix, Jean Michel Daga	A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	M. Templeton	Challenges and Opportunities Created by the SoC Shockwave.	MTDT	2002	DBLP BibTeX RDF
1	Luca Schiano, Cecilia Metra, Diego Marino	Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.	MTDT	2002	DBLP DOI BibTeX RDF
1	Toshiyuki Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye	Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process.	MTDT	2002	DBLP BibTeX RDF
1	Cyrille Dray, Philippe Gendrier	A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology.	MTDT	2002	DBLP DOI BibTeX RDF
1	Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née	An Automated Design Methodology for EEPROM Cell (ADE).	MTDT	2002	DBLP DOI BibTeX RDF
1	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	MTDT	2002	DBLP DOI BibTeX RDF
1	D. Bied-Charreton, D. Guillon, B. Jacques	The YATE Fail-Safe Interface: The User's Point of View.	MTDT	2002	DBLP DOI BibTeX RDF
1	Bernard Coloma, Patrick Delaunay, Olivier Husson	High Speed 15 ns 4 Mbits SRAM for Space Application.	MTDT	2002	DBLP DOI BibTeX RDF
1	Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi	Random Testing of Multi-Port Static Random Access Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu	Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch.	MTDT	2002	DBLP DOI BibTeX RDF
1	Romain Laffont, J. Razafindramora, Pierre Canet, Rachid Bouchakour, Jean-Michel Mirabel	Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact.	MTDT	2002	DBLP DOI BibTeX RDF

Publications at "MTDT"( http://dblp.L3S.de/Venues/MTDT )