| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Gaurav Rajavendra Reddy, Yiorgos Makris |
Design Space Exploration for Hotspot Detection.  |
MTV  |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sherif Hosny, Amr Baher |
Design Crawler: A Web Application for Digital Design Metadata Analysis. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Annachiara Ruospo, Ernesto Sánchez 0001 |
On the Detection of Always-On Hardware Trojans Supported by a Pre-Silicon Verification Methodology. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | |
20th International Workshop on Microprocessor/SoC Test, Security and Verification, MTV 2019, Austin, TX, USA, December 9-10, 2019 |
MTV |
2019 |
DBLP BibTeX RDF |
|
| 1 | Mikhail M. Chupilko, Alexander Kamkin, Alexander Protsenko |
Open-Source Validation Suite for RISC-V. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeff Scott, Jonathan Sadowsky, Jigar Savla |
RamGen: Moving Memories from Physical to the Logical Domain. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Prokash Ghosh, Rohit Srivastava |
Case Study: SoC Performance Verification and Static Verification of RTL Parameters. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinsae Jung, Jaeun Park, Apurva Kumar |
A Verification Framework of Neural Processing Unit for Super Resolution. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetas Mapara, Jerrin Jose |
Automated Test Picker for Complex Microprocessor Verification Environment. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mir Tanjidur Rahman, Navid Asadizanjani |
Backside Security Assessment of Modern SoCs. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Wahba, Justin Hohnerlein, Farhan Rahman |
Expediting Design Bug Discovery in Regressions of x86 Processors Using Machine Learning. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra |
Techniques for Debug of Low Power SoCs. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jigar Savla |
Smarter Disk Space Management for Silicon Workflows. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo |
Hardware and Software Co-Verification from Security Perspective. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib |
Multilayer Camouflaged Secure Boot for SoCs. |
MTV |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanhua Cao, Osama Shoubber, Pallavi Jesrani |
Automatic Debug Quantification for Workload Balance and Progress Tracking. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Asif Jafri, Jung-Wook Kim |
Proving the Capability of Arm IP for Functional Safety Applications. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mikhail M. Chupilko, Alexander Kamkin, Artem Kotsynyak, Alexander Protsenko, Sergey A. Smolov, Andrei Tatarnikov |
Test Program Generator MicroTESK for RISC-V. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetas Mapara, Priti Nagarajan |
Transaction Based Speedup for Simulation Replay. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Rekha Bangalore, Adeosun luwatosin Oluwatosin, Kelvin K. Lam |
Schmoo Data Analysis Using Machine Language Algorithms. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jigar Savla |
Getting Started on Co-Emulation: Transition your Design and Testbench to an Emulator. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Siroos Madani, Mohammad R. Madani, Magdy A. Bayoumi |
A Perceptron-Inspired Technique for Hardware Obfuscation. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelfattah Munir, Mina Magdy, Samer Ahmed, Sherouk Nasr, Sameh El-Ashry, Ahmed Shalaby 0001 |
Fast Reliable Verification Methodology for RISC-V Without a Reference Model. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Kumar Agarwal, Amandeep Sharan, Mohammad Asif Khan 0002, Atul Gupta |
Multi-Master Validation Framework for Next Generation Automotive SOCs. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | |
19th International Workshop on Microprocessor and SOC Test and Verification, MTV 2018, Austin, TX, USA, December 9-10, 2018 |
MTV |
2018 |
DBLP BibTeX RDF |
|
| 1 | Rekha Bangalore, Raji M. Bandanapudi |
Application of Combinatorial Test (CT) Algorithm for Protocol and Hardware Feature Validation. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayushi Agarwal, Pankaj Gupta, Atul Gupta |
Advanced Regression Management for Post-Silicon Validation of Automotive SOCs. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Shelly Henry, Nirabh Regmi |
How to Close Coverage 10x Faster using Portable Stimulus Standard - A Case Study. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Pratheema Mohandoss, Archana Rengaraj |
Pre-Silicon DFT Verification on SOC Slim Model. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Calvin Deutschbein, Cynthia Sturton |
Mining Security Critical Linear Temporal Logic Specifications for Processors. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sameh El-Ashry, Ahmed Adel |
Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Harry Foster |
2018 FPGA Functional Verification Trends. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr Moursi, Romaisaa Samhoud, Yaseen Kamal, Mazen Magdy, Sameh El-Ashry, Ahmed Shalaby 0001 |
Different Reference Models for UVM Environment to Speed Up the Verification Time. |
MTV |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Hu 0008, Armaiti Ardeshiricham, Ryan Kastner |
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Wahba, Justin Hohnerlein, Farhan Rahman, Li-C. Wang |
Dynamic Exerciser Template Weighting in x86 Processor Verification. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Fajcik, Pavel Smrz, Marcela Zachariásová |
Automation of Processor Verification Using Recurrent Neural Networks. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Nelson 0004, Peter-Michael Seidel |
Modeling and Analysis of Secure Processor Extensions Based on Actor Networks. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled Salah 0001 |
A Unified UVM Architecture for Flash-Based Memory. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | |
18th International Workshop on Microprocessor and SOC Test and Verification, MTV 2017, Austin, TX, USA, December 11-12, 2017 |
MTV |
2017 |
DBLP BibTeX RDF |
|
| 1 | Jack Lawrence Mason |
Validation of Context Preserving Thread-Level Speculative Execution Using N-Queens: Comparison of Non-CPSE and CPSE-enabled Applications. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand Raman, Yorgos Koutsoyannopoulos, Magdy Abadir |
Electromagnetic (EM) Crosstalk Failures and Symptoms in SoC Designs. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mikhail M. Chupilko, Alexander Kamkin, Artem Kotsynyak, Alexander Protsenko, Sergey A. Smolov, Andrei Tatarnikov |
Maintaining ISA Specifications in MicroTESK Test Program Generator. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhukarreddy Pappireddy, Bipin Ravi |
SequenceLanguage: A Constraint Random MP-RIS Generation Framework. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Abdel-Haleem, Magdy A. El-Moursy |
TLM Virtual Platform for Fast and Accurate Power Estimation. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Liting Yu, Xiaoxiao Wang 0001, Fahim Rahman, Mark M. Tehranipoor |
iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Gopalakrishnan, Bipin Ravi |
Anvil: Best in Class Multiprocessor Coherency Verification Tool. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahim Rahman, Mohammad Farmani, Mark M. Tehranipoor, Yier Jin |
Hardware-Assisted Cybersecurity for IoT Devices. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Siroos Madani, Magdy A. Bayoumi |
A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits. |
MTV |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar Amin, Youssef Ramzy, Omar Ibrahem, Ahmed Fouad 0001, Khaled Mohamed, Mohamed Abdelsalam |
System Verilog Assertions Synthesis Based Compiler. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Senwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak |
A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra 0001, Yier Jin |
Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed El-Yamany, Sameh El-Ashry, Khaled Salah 0001 |
Coverage Closure Efficient UVM Based Generic Verification Architecture for Flash Memory Controllers. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sainath Karlapalem, Shashank Venugopal |
Scalable, Constrained Random Software Driven Verification. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Xie, Chongxi Bao, Yuntao Liu 0001, Ankur Srivastava 0001 |
2.5D/3D Integration Technologies for Circuit Obfuscation. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vibarajan Viswanathan, Juliet Runhaar, Doug Reed, Jun Zhao |
Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled Fathy, Khaled Salah 0001 |
An Efficient Scenario Based Testing Methodology Using UVM. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Haytham Saafan, M. Watheq El-Kharashi, Ashraf Salem |
Formal Based Methodology for Inferring Memory Mapped Registers. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr B. Darwish, Magdy A. El-Moursy, Mohamed Dessouky |
Transaction Level Power Modeling (TLPM) Methodology. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Liwei Zhou, Yiorgos Makris |
Hardware-Based Workload Forensics and Malware Detection in Microprocessors. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Hu 0008, Alric Althoff, Armita Ardeshiricham, Ryan Kastner |
Towards Property Driven Hardware Security. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Saddam Jamil Quirem, Prasad Krishna Saravu |
Fake CPU: A Flexible and Simulation Cost-Effective UVC for Testing Shared Caches. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | |
17th International Workshop on Microprocessor and SOC Test and Verification, MTV 2016, Austin, TX, USA, December 12-13, 2016 |
MTV |
2016 |
DBLP BibTeX RDF |
|
| 1 | Prasad Krishna Saravu |
Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed El-Yamany |
Echoing the "Generality Concept" through the Bus Functional Model Architecture in Universal Verification Environments. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amandeep Sharan, Ashish Gupta |
Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mikhail M. Chupilko, Alexander S. Kamkin, Artem Kotsynyak, Alexander Protsenko, Sergey A. Smolov, Andrei Tatarnikov |
Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaolong Guo, Raj Gautam Dutta, Yier Jin |
Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Nelson 0004, Peter-Michael Seidel |
Modeling and Analysis of Trusted Boot Processes Based on Actor Network Procedures. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Harshit Goyal, Vishwani D. Agrawal |
Characterizing Processors for Energy and Performance Management. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourav Roy, Nikhil Jain, Sandeep Jain, Robert Page |
Leveraging Virtual Prototype Models for Hardware Verification of an Accelerated Network Packet Processing Engine. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Bicky Shakya, Fahim Rahman, Mark M. Tehranipoor, Domenic Forte |
Harnessing Nanoscale Device Properties for Hardware Security. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy Ridgeway |
Performance of a SystemVerilog Sudoku Solver with VCS. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Taylor Holmes, Andrew Passerelli, John Connor |
SoC Development and Prototype with VDK. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | John Hudson, Gunaranjan Kurucheti |
Enhancing the Stress and Efficiency of RIS Tools Using Coverage Metrics. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | |
16th International Workshop on Microprocessor and SOC Test and Verification, MTV 2015, Austin, TX, USA, December 3-4, 2015 |
MTV |
2015 |
DBLP BibTeX RDF |
|
| 1 | Daniel Hansson |
Automatic Bug Fixing. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed A. Salem, Kerstin I. Eder |
Novel MC/DC Coverage Test Sets Generation Algorithm, and MC/DC Design Fault Detection Strength Insights. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Rico Angell, Ben Oztalay, Andrew DeOrio |
A Topological Approach to Hardware Bug Triage. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Zdenek Prikryl |
Fast Simulation of Pipeline in ASIP Simulators. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Venkatesan, Pradeep Nagarajan |
A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Michele Lora, Francesco Martinelli, Franco Fummi |
Hardware Synthesis from Software-Oriented UML Descriptions. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Mefenza, Franck Yonga, Christophe Bobda |
Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC Designs. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed O. Kayed, Mohamed Abdelsalam, Rafik Guindi |
A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Weihua Han |
Improve the Verification Productivity: Some Best Practices from SoC and Processor Projects. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | John Hudson, Gunaranjan Kurucheti |
A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor Systems. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Hansson |
Continuous Linting with Automatic Debug. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Parikshit Pritam Dhodapkar |
Synthesizable Memory Models for Virtual Prototyping. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Venkatakrishnan, Naresh Kumar Kadali |
'Dump What You Need' - A Coverage Methodology to Accelerate SoC Verification. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Banerjee 0003, Tushar Gupta |
Optimized Simulation Acceleration with Partial Testbench Evaluation. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky |
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Nitin Gupta, Chethan Harakchand |
Embracing the FPGA Challenge for Processor Design Verification. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter-Michael Seidel |
Directed Test Case Generation for x86 Instruction Decoding. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | |
15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014 |
MTV |
2014 |
DBLP BibTeX RDF |
|
| 1 | Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey |
Mutation Based Feature Localization. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukás Charvát, Ales Smrcka, Tomás Vojnar |
Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Shajid Thiruvathodi, Deepak Yeggina |
A Random Instruction Sequence Generator for ARM Based Systems. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Höller, Gerhard Schonfelder, Nermin Kajtazovic, Tobias Rauter, Christian Kreiner |
FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical Systems. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Maneesh Kumar Pandey, Shwetank Shekhar, Amit Sinha, Arun Mishra |
An FPGA Based Ecosystem for USBPHY Validation. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter-Michael Seidel |
A Case for Multi-level Combination of Theorem Proving and Model Checking Tools. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Mrugesh Walimbe |
JTAG-AXI Debug IP with Performance Meter Mode. |
MTV |
2014 |
DBLP DOI BibTeX RDF |
|
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