Search results for "SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala	Customizable Datapath Integrated Lock Unit.	SoC	2011	DBLP DOI BibTeX RDF
1		2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011	SoC	2011	DBLP BibTeX RDF
1	Daniele Bortolotti, Francesco Paterna, Christian Pinto, Andrea Marongiu, Martino Ruggiero, Luca Benini	Exploring instruction caching strategies for tightly-coupled shared-memory clusters.	SoC	2011	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser	A system level power consumption estimation for MPSoC.	SoC	2011	DBLP DOI BibTeX RDF
1	Firew Siyoum, Marc Geilen, Orlando Moreira, Rick J. M. Nas, Henk Corporaal	Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications.	SoC	2011	DBLP DOI BibTeX RDF
1	Tomoki Ikegaya, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima	A hybrid model of speculative execution and scout threading for auto-memoization processor.	SoC	2011	DBLP DOI BibTeX RDF
1	Claudio Brunelli, Eero Aho, Heikki Berg	OpenCL implementation of Cholesky matrix decomposition.	SoC	2011	DBLP DOI BibTeX RDF
1	Christoph Schmutzler, Abdallah Lakhtel, Martin Simons 0001, Jürgen Becker 0001	Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay.	SoC	2011	DBLP DOI BibTeX RDF
1	Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny	Mismatch characterization of high-speed NoC links using asynchronous sub-sampling.	SoC	2011	DBLP DOI BibTeX RDF
1	Issam W. Damaj	Co-designs of parallel Rijndael.	SoC	2011	DBLP DOI BibTeX RDF
1	Omer Malik, Ahmed Hemani	Synchronizing distributed state machines in a coarse grain reconfigurable architecture.	SoC	2011	DBLP DOI BibTeX RDF
1	Marco Ferraresi, Giuseppina Gobbo, Daniele Ludovici, Davide Bertozzi	Bringing Network-on-Chip links to 45nm.	SoC	2011	DBLP DOI BibTeX RDF
1	Mohammad Badawi, Ahmed Hemani	A coarse-grained reconfigurable protocol processor.	SoC	2011	DBLP DOI BibTeX RDF
1	Teodor Tite, Adelina Vig, Nicolae Olteanu, Cristian Cuna	moviTest: A Test Environment dedicated to multi-core embedded architectures.	SoC	2011	DBLP DOI BibTeX RDF
1	Subayal Khan, Jukka Saastamoinen, Mikko Majanen, Jyrki Huusko, Jari Nurmi	Analyzing transport and MAC layer in system-level performance simulation.	SoC	2011	DBLP DOI BibTeX RDF
1	Milos Krstic, Xin Fan 0003, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi	Moonrake chip - GALS demonstrator in 40 nm CMOS technology.	SoC	2011	DBLP DOI BibTeX RDF
1	Mikhail J. Moiseev, Alexey V. Zakharov, Ilya Klotchkov, Sergey I. Salishev	Static analysis method for deadlock detection in SystemC designs.	SoC	2011	DBLP DOI BibTeX RDF
1	Mehdi Modarressi, Seyed Hossein Nikounia, Amir Hossein Jahangir	Low-power arithmetic unit for DSP applications.	SoC	2011	DBLP DOI BibTeX RDF
1	Vladimír Guzma, Teemu Pitkänen, Jarmo Takala	Effects of loop unrolling and use of instruction buffer on processor energy consumption.	SoC	2011	DBLP DOI BibTeX RDF
1	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001, Jaime Jimenez, Aitzol Zuloaga	An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS.	SoC	2011	DBLP DOI BibTeX RDF
1	Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen	Applying IP-XACT in product data management.	SoC	2011	DBLP DOI BibTeX RDF
1	Zubair Wadood Bhatti, Davy Preuveneers, Yolande Berbers, Narasinga Rao Miniskar, Roel Wuyts	SAMOSA: Scratchpad aware mapping of streaming applications.	SoC	2011	DBLP DOI BibTeX RDF
1	Esko Pekkarinen, Lasse Lehtonen, Erno Salminen, Timo D. Hämäläinen	A set of traffic models for Network-on-Chip benchmarking.	SoC	2011	DBLP DOI BibTeX RDF
1	Tim Wegner, Martin Gag, Dirk Timmermann	Impact of proactive temperature management on performance of Networks-on-Chip.	SoC	2011	DBLP DOI BibTeX RDF
1	Yaset Oliva, Maxime Pelcat, Jean-François Nezan, Jean-Christophe Prévotet, Slaheddine Aridhi	Building a RTOS for MPSoC dataflow programming.	SoC	2011	DBLP DOI BibTeX RDF
1	Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid	Automatic calibration of streaming applications for software mapping exploration.	SoC	2011	DBLP DOI BibTeX RDF
1	Rainer Findenig, Wolfgang Ecker	State chart refinement validation from approximately timed to cycle callable models.	SoC	2010	DBLP DOI BibTeX RDF
1	Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi	Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.	SoC	2010	DBLP DOI BibTeX RDF
1	Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout	Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.	SoC	2010	DBLP DOI BibTeX RDF
1	Kris Heyrman, Peter Veelaert	Useful-state encoding: Network control with minimal redundancy.	SoC	2010	DBLP DOI BibTeX RDF
1	Vladimír Guzma, Teemu Pitkänen, Jarmo Takala	Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis.	SoC	2010	DBLP DOI BibTeX RDF
1	Joonas Tyystjärvi, Tero Säntti, Juha Plosila	Heap access optimizations for a hardware-accelerated Java virtual machine.	SoC	2010	DBLP DOI BibTeX RDF
1	Tomi Aarnio, Claudio Brunelli, Timo Viitanen	Efficient floating-point texture decompression.	SoC	2010	DBLP DOI BibTeX RDF
1	Tiago Dias 0001, Nuno Roma, Leonel Sousa	H.264/AVC framework for multi-core embedded video encoders.	SoC	2010	DBLP DOI BibTeX RDF
1	Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta	Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method.	SoC	2010	DBLP DOI BibTeX RDF
1	Alexander Klimm, Matthias Haas, Oliver Sander, Jürgen Becker 0001	A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography.	SoC	2010	DBLP DOI BibTeX RDF
1	Ingo Rust, Tobias G. Noll	A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point.	SoC	2010	DBLP DOI BibTeX RDF
1	Zulfiqar Ali 0002, Ali Arshad, Umair Razzaq, Sawaira Sana, Abdul Haseeb Ahmed, Abdullah M. Harris	Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm.	SoC	2010	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Thiago R. da Rosa, Fernando Gehm Moraes	A message-level monitoring protocol for QoS flows in NoCs.	SoC	2010	DBLP DOI BibTeX RDF
1	Claudio Brunelli, Roberto Airoldi, Jari Nurmi	Implementation and benchmarking of FFT algorithms on multicore platforms.	SoC	2010	DBLP DOI BibTeX RDF
1	Waqar Hussain 0001, Fabio Garzia, Jari Nurmi	Exploiting control management to accelerate Radix-4 FFT on a reconfigurable platform.	SoC	2010	DBLP DOI BibTeX RDF
1	Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi	Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.	SoC	2010	DBLP DOI BibTeX RDF
1	Thomas Coenen, Jochen Schleifer, Oliver Weiß, Tobias G. Noll	Interconnect routing of embedded FPGAs using standard VLSI routing tools.	SoC	2010	DBLP DOI BibTeX RDF
1	Matthias Korb, Tobias G. Noll	LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates.	SoC	2010	DBLP DOI BibTeX RDF
1	Sebastian Höppner, Dennis Walter, Holger Eisenreich, René Schüffny	Efficient compensation of delay variations in high-speed network-on-chip data links.	SoC	2010	DBLP DOI BibTeX RDF
1	Pallavi Reddy, Fabien Clermidy, Rasheed Al Khayat, Amer Baghdadi, Michel Jézéquel	Power consumption analysis and energy efficient optimization for turbo decoder implementation.	SoC	2010	DBLP DOI BibTeX RDF
1	Roberto Airoldi, Fabio Garzia, Omer Anjum, Jari Nurmi	Homogeneous MPSoC as baseband signal processing engine for OFDM systems.	SoC	2010	DBLP DOI BibTeX RDF
1	Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser	Correct and energy-efficient design of SoCs: The H.264 encoder case study.	SoC	2010	DBLP DOI BibTeX RDF
1	Piia Saastamoinen, Jari Nurmi	Parameterized decompression hardware for a program memory compression system.	SoC	2010	DBLP DOI BibTeX RDF
1	Spencer S. Kellis, Nathaniel Gaskin, Bennion Redd, Eric D. Marsman, Richard Brown 0003	Hybrid on-chip clocking for sensor nodes.	SoC	2010	DBLP DOI BibTeX RDF
1	Chris Jackson, Simon J. Hollis	Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs.	SoC	2010	DBLP DOI BibTeX RDF
1	Samarjit Chakraborty	Multiprocessor system and software design for distributed control applications.	SoC	2010	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi	A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II.	SoC	2010	DBLP DOI BibTeX RDF
1	Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid	EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures.	SoC	2010	DBLP DOI BibTeX RDF
1	Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir, Muhammad Faisal Nadeem, Fakhar Anjam	Low-power, high-throughput deblocking filter for H.264/AVC.	SoC	2010	DBLP DOI BibTeX RDF
1	Nguyen Anh Vu Doan, Frédéric Robert, Yves De Smet, Dragomir Milojevic	MCDA-based methodology for efficient 3D-design space exploration and decision.	SoC	2010	DBLP DOI BibTeX RDF
1	Lasse Määttä, Jukka Suhonen, Teemu Laukkarinen, Timo D. Hämäläinen, Marko Hännikäinen	Program image dissemination protocol for low-energy multihop wireless sensor networks.	SoC	2010	DBLP DOI BibTeX RDF
1	Andreas Genser, Christian Bachmann, Christian Steger, Reinhold Weiss, Josef Haid	Power emulation based DVFS efficiency investigations for embedded systems.	SoC	2010	DBLP DOI BibTeX RDF
1	Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang 0002	On-line dependability enhancement of multiprocessor SoCs by resource management.	SoC	2010	DBLP DOI BibTeX RDF
1	Guang Sun, Yong Li 0008, Yuanyuan Zhang, Li Su 0001, Depeng Jin, Lieguang Zeng	Energy-aware run-time mapping for homogeneous NoC.	SoC	2010	DBLP DOI BibTeX RDF
1		2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010	SoC	2010	DBLP BibTeX RDF
1	Subayal Khan, Eila Ovaska, Kari Tiensyrjä, Jari Nurmi	From Y-chart to seamless integration of application design and performance simulation.	SoC	2010	DBLP DOI BibTeX RDF
1	Di Wu 0003, Johan Eilert, Dake Liu, Anders Nilsson 0001, Eric Tell, Eric Alfredsson	System architecture for 3GPP LTE modem using a programmable baseband processor.	SoC	2009	DBLP DOI BibTeX RDF
1	Faiz-ul Hassan, B. Cheng, Wim Vanderbauwhede, Fernando Rodríguez Salazar	Impact of device variability in the communication structures for future synchronous SoC designs.	SoC	2009	DBLP DOI BibTeX RDF
1	Tor Skeie, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, José Flich, Davide Bertozzi, Simone Medardoni	Flexible DOR routing for virtualization of multicore chips.	SoC	2009	DBLP DOI BibTeX RDF
1	Volker Gierenz, Christian Panis, Jari Nurmi	Physical realization oriented area-power-delay tradeoff exploration.	SoC	2009	DBLP DOI BibTeX RDF
1	Haitham Habli, Johan Lilius, Johan Ersfolk	Analysis of memory access optimization for motion compensation frames in MPEG-4.	SoC	2009	DBLP DOI BibTeX RDF
1	Davide Rossi, Fabio Campi, Antonio Deledda, Claudio Mucci, Stefano Pucillo, Sean Whitty, Rolf Ernst, Stéphane Chevobbe, Stéphane Guyetant, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001, Wolfram Putzke-Röming	A multi-core signal processor for heterogeneous reconfigurable computing.	SoC	2009	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, César A. M. Marcon, Ney Calazans, Fernando Moraes 0001	Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs.	SoC	2009	DBLP DOI BibTeX RDF
1	Mihkel Tagel, Peeter Ellervee, Gert Jervan	Scheduling framework for real-time dependable NoC-based systems.	SoC	2009	DBLP DOI BibTeX RDF
1	Heikki Kariniemi, Jari Nurmi	Fault-tolerant communication over Micronmesh NOC with Micron Message-Passing protocol.	SoC	2009	DBLP DOI BibTeX RDF
1	Heikki Orsila, Erno Salminen, Timo D. Hämäläinen	Parameterizing simulated annealing for distributing Kahn Process Networks on multiprocessor SoCs.	SoC	2009	DBLP DOI BibTeX RDF
1	Marco Lattuada 0001, Christian Pilato, Antonino Tumeo, Fabrizio Ferrandi	Performance modeling of parallel applications on MPSoCs.	SoC	2009	DBLP DOI BibTeX RDF
1	Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward	Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms.	SoC	2009	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi	Characterising embedded applications using a UML profile.	SoC	2009	DBLP DOI BibTeX RDF
1	Joël Porquet, Christian Schwarz, Alain Greiner	Multi-compartment: A new architecture for secure co-hosting on SoC.	SoC	2009	DBLP DOI BibTeX RDF
1	Zhenyu Tu, Meng Yu 0002, Daniel Iancu, Mayan Moudgill, John Glossner	On the performance of 3GPP LTE baseband using SB3500.	SoC	2009	DBLP DOI BibTeX RDF
1	Wei Song 0002, Doug A. Edwards	Building asynchronous routers with independent sub-channels.	SoC	2009	DBLP DOI BibTeX RDF
1	Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp	A checkpoint/restore framework for systemc-based virtual platforms.	SoC	2009	DBLP DOI BibTeX RDF
1	Behnam Ghavami, Hamid R. Zarandi, Arezoo Salarpour, Hossein Pedram	Diagnosis of faults in template-based asynchronous circuits.	SoC	2009	DBLP DOI BibTeX RDF
1	Eric P. Kim, Rami A. Abdallah, Naresh R. Shanbhag	Soft NMR: Exploiting statistics for energy-efficiency.	SoC	2009	DBLP DOI BibTeX RDF
1	Aleksandar Milutinovic, Kees Goossens, Gerard J. M. Smit	Dynamic workload peak detection for slack management.	SoC	2009	DBLP DOI BibTeX RDF
1	Kshitij Bhardwaj, Rabindra Ku Jena	Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms.	SoC	2009	DBLP DOI BibTeX RDF
1	David Szczesny, Anas Showk, Sebastian Hessel, Attila Bilgic, Uwe Hildebrand, Valerio Frascolla	Performance analysis of LTE protocol processing on an ARM based mobile platform.	SoC	2009	DBLP DOI BibTeX RDF
1	Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine	Two phase clocked adiabatic static CMOS logic.	SoC	2009	DBLP DOI BibTeX RDF
1		2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008	SoC	2009	DBLP BibTeX RDF
1	Piia Saastamoinen, Jari Nurmi, Ilkka Saastamoinen, Mikko Laiho	Minimizing area costs in GPS applications on a programmable DSP by code compression.	SoC	2009	DBLP DOI BibTeX RDF
1	Dragomir Milojevic, Riko Radojcic, Roger Carpenter, Pol Marchal	Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits.	SoC	2009	DBLP DOI BibTeX RDF
1	Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna	Performance analysis of multi-channel memories in mobile devices.	SoC	2009	DBLP DOI BibTeX RDF
1	David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay	Automatic generation of memory interfaces.	SoC	2009	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink	An efficient software cache for H.264 motion compensation.	SoC	2009	DBLP DOI BibTeX RDF
1	Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede	Automated instrumentation of FPGA-based systems for system-level transaction monitoring.	SoC	2009	DBLP DOI BibTeX RDF
1	Fabio Campi, Ralf König 0001, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner 0001, Jürgen Becker 0001, Roberto Guerrieri	RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.	SoC	2009	DBLP DOI BibTeX RDF
1	Chris Rowen, Peter R. Nuth, Stuart Fiske	A DSP architecture optimized for wireless baseband.	SoC	2009	DBLP DOI BibTeX RDF
1	Fabio Garzia, Roberto Airoldi, Jari Nurmi, Carmelo Giliberto, Claudio Brunelli	Mapping of the FFT on a reconfigurable architecture targeted to SDR applications.	SoC	2009	DBLP DOI BibTeX RDF
1	Samuel Rodrigo, Carles Hernández 0001, José Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai	Yield-oriented evaluation methodology of network-on-chip routing implementations.	SoC	2009	DBLP DOI BibTeX RDF
1	Matthias Eireiner, Doris Schmitt-Landsiedel, Paul Wallner, Andreas Schöne, Stephan Henzler, Ulrich Fiedler	Adaptive circuit block model for power supply noise analysis of low power system-on-chip.	SoC	2009	DBLP DOI BibTeX RDF
1	Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch	Instruction merging to increase parallelism in VLIW architectures.	SoC	2009	DBLP DOI BibTeX RDF
1	Erno Salminen, Ari Kulmala, Timo Hämäläinen 0001	On the credibility of load-latency measurement of network-on-chips.	SoC	2008	DBLP DOI BibTeX RDF
1	Heikki Hurskainen, Jussi Raasakka, Jari Nurmi	Specification of GNSS application for multiprocessor platform.	SoC	2008	DBLP DOI BibTeX RDF

Publications at "SoC"( http://dblp.L3S.de/Venues/SoC )