Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link
1	YunKyung Lee, YoungSu Park	High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card.	VLSI	2003	DBLP BibTeX RDF
1	Yiming Li 0005, Shao-Ming Yu, Hsiao-Mei Lu	Intelligent Device Parameter Extraction for Nanoscale MOSFETs Era.	VLSI	2003	DBLP BibTeX RDF
1	Mitra Mirhassani, Majid Ahmadi, William C. Miller	A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays.	VLSI	2003	DBLP BibTeX RDF
1	J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim	Properties of A1/BaTa2O6/GaN MIS Structure.	VLSI	2003	DBLP BibTeX RDF
1	Yil Suk Yang, Jongdae Kim, Tae Moon Roh, Dae Wood Lee, Sung-Ku Kwon, Il Yong Park, Byoung Gon Yu	Level Shifter Circuit Having Dual Outputs for FPD Gate Driver.	VLSI	2003	DBLP BibTeX RDF
1	Shih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li	Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides.	VLSI	2003	DBLP BibTeX RDF
1	Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi	Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design.	VLSI	2003	DBLP BibTeX RDF
1	Jae-Young Yi, Yong-Hui Lee, Cheon-Hee Yi	PEDE (Plasma Edge Damage Effect) Curing by Various Heat Treatment.	VLSI	2003	DBLP BibTeX RDF
1	Thomas Eschbach, Wolfgang Günther 0001, Bernd Becker 0001	Cross Reduction for Orthogonal Circuit Visualization.	VLSI	2003	DBLP BibTeX RDF
1	Scott F. Smith 0002	The Advanced Encryption Standard on an Asynchronous Shared-Memory Multiprocessor.	VLSI	2003	DBLP BibTeX RDF
1	Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown	Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices.	VLSI	2003	DBLP BibTeX RDF
1	Keun Soo Yim, Kern Koh, Hyokyung Bahn	A Compressed Page Management Scheme for NAND-Type Flash Memory.	VLSI	2003	DBLP BibTeX RDF
1	Noboru Watanabe	Foundation of Quantum Capacity.	VLSI	2003	DBLP BibTeX RDF
1	Gene Eu Jan, Chiou-Min Shen, Shao-Wei Leu, Cheng-Hung Li	The Design and Analysis of an Elliptic Curve Cryptosystem.	VLSI	2003	DBLP BibTeX RDF
1	Scott C. Smith	Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy.	VLSI	2003	DBLP BibTeX RDF
1	Hirotsuga Kajisaki, Takakazu Kurokawa	SEBSW-2: SEcret-Key Block Cipher SWitcher.	VLSI	2003	DBLP BibTeX RDF
1	Ali Telli, Simsek Demir, Murat Askar	Planar Spiral Inductor Modeling for RFIC Design.	VLSI	2003	DBLP BibTeX RDF
1	Mitchell J. Myjak, José G. Delgado-Frias	A Two-Level Reconfigurable Architecture for Digital Signal Processing.	VLSI	2003	DBLP BibTeX RDF
1	Jie Han 0001, Pieter Jonker	A Study on Fault-Tolerant Circuits Using Redundancy.	VLSI	2003	DBLP BibTeX RDF
1	Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker	An Area-Efficient Bit-Serial Integer Multiplier.	VLSI	2003	DBLP BibTeX RDF
1	Fred L. Anderson IV, José G. Delgado-Frias	A Reconfigurable Switch for a DSP Array.	VLSI	2003	DBLP BibTeX RDF
1	Jaime Ramírez-Angulo, Chandrika Durbha, Gladys Omayra Ducoudray, Ramón González Carvajal	Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion.	VLSI	2003	DBLP BibTeX RDF
1	Adnan M. Lokhandwala, Sudip K. Mazumder	A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters.	VLSI	2003	DBLP BibTeX RDF
1	X. Zhang, Gabriel Dragffy, Anthony G. Pipe	Bio-Inspired Reconfigurable Architecture for Reliable Systems.	VLSI	2003	DBLP BibTeX RDF
1	Nathaniel Bird, Ethan S. Miller, Paul J. Pfeiffer, Srinivasa Vemuru	Channel Routing with Crosstalk Consideration.	VLSI	2003	DBLP BibTeX RDF
1	Luigi Accardi, Masanori Ohya	A Stochastic Limit Approach to the SAT Problem.	VLSI	2003	DBLP BibTeX RDF
1	Kang Hyeon Rhee	A Study on the 8bit Pipeline RISC Processor.	VLSI	2003	DBLP BibTeX RDF
1	Rita M. Hare, Bryant A. Julstrom	A Genetic Algorithm for Restricted Cases of the Rectilinear Steiner Problem with Obstacles.	VLSI	2003	DBLP BibTeX RDF
1	Todd W. Neller, David C. Hettlinger	Learning Annealing Schedules for Channel Routing.	VLSI	2003	DBLP BibTeX RDF
1	Suleyman Tosun, Hakduran Koc, Nazanin Mansouri	Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs.	VLSI	2003	DBLP BibTeX RDF
1	Vishal Verma, Himanshu Thapliyal	A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics.	VLSI	2003	DBLP BibTeX RDF
1	Jam Wem Lee, Yiming Li, Howard Tang	Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design.	VLSI	2003	DBLP BibTeX RDF
1	Daniel R. Blum, José G. Delgado-Frias	A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor.	VLSI	2003	DBLP BibTeX RDF
1	Andris Ambainis, Uldis Barbans, Agnese Belousova, Aleksandrs Belovs, Ilze Dzelme, Girts Folkmanis, Rusins Freivalds, Peteris Ledins, Rihards Opmanis, Agnis Skuskovniks	Size of Quantum Versus Deterministic Finite Automata.	VLSI	2003	DBLP BibTeX RDF
1	Amardeep Singh	Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing.	VLSI	2003	DBLP BibTeX RDF
1	Hamid R. Arabnia, Laurence Tianruo Yang (eds.)	Proceedings of the International Conference on VLSI, VLSI '03, June 23 - 26, 2003, Las Vegas, Nevada, USA	VLSI	2003	DBLP BibTeX RDF
1	Gene Eu Jan, Lokar J. Y. Lin, W. R. Liou, Y. Y. Chen	The Design and Implementation of a 2048-Bit RSA Encryption/Decryption Chip.	VLSI	2003	DBLP BibTeX RDF
1	L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti 0001, Sivaprakasam Suresh	On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems.	VLSI	2003	DBLP BibTeX RDF
1	Christian Panis, Gunther Laure, Wolfgang Lazian, Herbert Grünbacher, Jari Nurmi	A Branch File for a Configurable DSP Core.	VLSI	2003	DBLP BibTeX RDF
1	Hoon Na, Dae-Gwon Jeong	MPEG-4 HVXC Real-Time Implementation on Floating Point DSP.	VLSI	2003	DBLP BibTeX RDF
1	Satoshi Ikeda, Izumi Kubo, Masafumi Yamashita	Reducing the Hitting and the Cover Times of Random Walks on Finite Graphs by Local Topological Information.	VLSI	2003	DBLP BibTeX RDF
1	Hussain Al-Asaad, Alireza Sarvi	Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling.	VLSI	2003	DBLP BibTeX RDF
1	Seung Wook Lee, Jong Tae Kim	Universal Reed-Solomon Decoder Using Hardware/Software Co-Design Method.	VLSI	2003	DBLP BibTeX RDF
1	Janet Meiling Wang, Pinhong Chen, Omar Hafiz	Switching Windows Computation in Presence of Crosstalk Noise.	VLSI	2003	DBLP BibTeX RDF
1	Ling Wang 0004, Yingtao Jiang, Henry Selvaraj	Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints.	VLSI	2003	DBLP BibTeX RDF
1	Deshanand P. Singh, Stephen Dean Brown	An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion.	VLSI	2003	DBLP BibTeX RDF
1	Sankalp Kallakuri, Alex Doboli, Simona Doboli	Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems.	VLSI	2003	DBLP BibTeX RDF
1	Naresh Sarwabhotla, Arthi Kothandaraman	A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated Circuits.	VLSI	2003	DBLP BibTeX RDF
1	Bhupen P. Zaveri	Phase Coincidence Technique for Frequency Difference Measurement.	VLSI	2003	DBLP BibTeX RDF
1	Satish K. Bandapati, Scott C. Smith	Design and Characterization of NULL Convention Arithmetic Logic Units.	VLSI	2003	DBLP BibTeX RDF
1	Volnei A. Pedroni	High-Resolution WTA-MAX Circuit for Large Networks.	VLSI	2003	DBLP BibTeX RDF
1	Anilkumar Patro, Ashish Mishra	Lower Power Processor Design Issues.	VLSI	2003	DBLP BibTeX RDF
1	Manfred Schimmler, Viktor Bunimov	A Simple Circuit to Reduce the Search Range for Large Prime Numbers.	VLSI	2003	DBLP BibTeX RDF
1	Jiyi Gu, Majid Ahmadi, William C. Miller	A Low-Voltage Low-Power Digital-Audio Sigma-Delta Modulator in 0.18-µm CMOS.	VLSI	2003	DBLP BibTeX RDF
1	Robert Chun, Linda Yang 0001	Reuse of Firmware Tests in System-On-Chip Design Verification.	VLSI	2003	DBLP BibTeX RDF
1	Arifur Rahman	Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current.	VLSI	2003	DBLP BibTeX RDF
1	Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang	A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File.	VLSI	2003	DBLP BibTeX RDF
1	Jaime Ramírez-Angulo, Shanta Thoutam, Gladys Omayra Ducoudray, Ramón González Carvajal	A New Power Efficient Fully Differential Low-Voltage Two Stage OP-AMP Architecture.	VLSI	2003	DBLP BibTeX RDF
1	Lelde Lace, Rusins Freivalds	Lower Bounds for Query Complexity of Some Graph Problems.	VLSI	2003	DBLP BibTeX RDF
1	Srinivasa Vemuru	Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitance.	VLSI	2003	DBLP BibTeX RDF
1	Evandro de Araújo Jardini, Dilvan de Abreu Moreira	Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2.	VLSI	2003	DBLP BibTeX RDF
1	Youngsoo Kim, Janghong Yoon, Sungok Kim	An Improved Circuit Design for Parallel Sequence Generation.	VLSI	2003	DBLP BibTeX RDF
1	L. Miguel Silveira, Srinivas Devadas, Ricardo Augusto da Luz Reis (eds.)	VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal	VLSI	2000	DBLP BibTeX RDF
1	Maria-Cristina V. Marinescu, Martin C. Rinard	A Synthesis Algorithm for Modular Design of Pipelined Circuits.	VLSI	1999	DBLP BibTeX RDF
1	J. Soares Augusto, C. F. Beltrá Almeida	FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits.	VLSI	1999	DBLP BibTeX RDF
1	Rolf Drechsler, Wolfgang Günther 0001	History-Based Dynamic Minimization During BDD Construction.	VLSI	1999	DBLP BibTeX RDF
1	Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie	A Feature Associative Processor for Image Recognition Based on A-D merged Architecture.	VLSI	1999	DBLP BibTeX RDF
1	João M. S. Alcântara, Sergio C. Salomão, Edson do Prado Granja, Vladimir Castro Alves, Felipe M. G. França	Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation.	VLSI	1999	DBLP BibTeX RDF
1	Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick	Efficient RLC Macromodels for Digital IC Interconnect.	VLSI	1999	DBLP BibTeX RDF
1	João M. P. Cardoso, Horácio C. Neto	An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.	VLSI	1999	DBLP BibTeX RDF
1	Fernando Moraes 0001, Michel Robert, Daniel Auvergne	A Virtual CMOS Library Approach for East Layout Synthesis.	VLSI	1999	DBLP BibTeX RDF
1	Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang	Architectural Transformations for Hierarchical Algorithmic Descriptions.	VLSI	1999	DBLP BibTeX RDF
1	Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini	A Fast Parametric Model for Contact-Substrate Coupling.	VLSI	1999	DBLP BibTeX RDF
1	Rui L. Aguiar, Dinis M. Santos	Clock Distribution Strategy for IP-based Development.	VLSI	1999	DBLP BibTeX RDF
1	Franz Sischka	Device Modeling and Measurement for RF Systems.	VLSI	1999	DBLP BibTeX RDF
1	Christophe Jégo, Emmanuel Casseau, Eric Martin 0001	Architectural Synthesis with Interconnection Cost Control.	VLSI	1999	DBLP BibTeX RDF
1	Joonyoung Kim, João Marques-Silva 0001, Karem A. Sakallah	Satisfiability-Based Functional Delay Fault Testing.	VLSI	1999	DBLP BibTeX RDF
1	Camille Diou, Lionel Torres, Michel Robert	Implementation of a Wavelet Transform Architecture for Image Processing.	VLSI	1999	DBLP BibTeX RDF
1	R. Lerch, Manfred Kaltenbacher, H. Landes	CAE Environment for Electromechanical Microsystems.	VLSI	1999	DBLP BibTeX RDF
1	Stefan Thomas Obenaus, Ted H. Szymanski	Placements Benchmarks for 3-D VLSI.	VLSI	1999	DBLP BibTeX RDF
1	Raimund Ubar, Dominique Borrione	Design Error Diagnosis in Digital Circuits without Error Model.	VLSI	1999	DBLP BibTeX RDF
1	Rainer Brück 0001, Andreas Priebe, Kai Hahn	Cost Consideration for Application Specific Microsystems Physical Design Stages - A New Approach for Microtechnological Process Design.	VLSI	1999	DBLP BibTeX RDF
1	Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx	Scalable Run Time Reconfigurable Architecture.	VLSI	1999	DBLP BibTeX RDF
1	Fernanda Lima 0001, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis	Designing a Mask Programmable Matrix for Sequential Circuits.	VLSI	1999	DBLP BibTeX RDF
1	Bingxin Li, Hannu Tenhunen	A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process.	VLSI	1999	DBLP BibTeX RDF
1	A. M. Rassau, Geoffrey Alagoda, David Lucas, J. Austin-Crowe, Kamran Eshraghian	Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications.	VLSI	1999	DBLP BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	An IEEE Compliant Floating Point MAF.	VLSI	1999	DBLP BibTeX RDF
1	Flávio Rech Wagner, Márcio Oyamada, Luigi Carro, Márcio Eduardo Kreutz	Object-Oriented Modeling and Co-Simulation of Embedded Systems.	VLSI	1999	DBLP BibTeX RDF
1	Bartlomiej F. Romanowicz, M. Hasan Zaman, S. F. Bart, V. L. Rabinovich, I. Tchertkov, C. Hsu, John R. Gilbert	A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS.	VLSI	1999	DBLP BibTeX RDF
1	Yue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail 0001, Håkan K. Olsson	Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications.	VLSI	1999	DBLP BibTeX RDF
1	Tomohiro Yoneda	Verification of Abstracted Instruction Cache of TITAC2: A Case Study.	VLSI	1999	DBLP BibTeX RDF
1	Andreas Kirschbaum, Jürgen Becker 0001, Manfred Glesner	ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.	VLSI	1999	DBLP BibTeX RDF
1	S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres	Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.	VLSI	1999	DBLP BibTeX RDF
1	Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.	VLSI	1999	DBLP BibTeX RDF
1	James C. Hoe, Arvind	Hardware Synthesis from Term Rewriting Systems.	VLSI	1999	DBLP BibTeX RDF
1	Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Mark A. Hemming, Peter Holzmann, Oliver C. Kao, Chun Mai-Liu, Carl R. Palmer, Aditya Raina	An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices.	VLSI	1999	DBLP BibTeX RDF
1	David H. Albonesi	An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures.	VLSI	1999	DBLP BibTeX RDF
1	Joel R. Phillips, Dan Feng	Trends in RF Simulation Algorithms.	VLSI	1999	DBLP BibTeX RDF
1	Tom Chen 0001, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar	Efficient Verification of Behavioral Models Using Sequential Sampling Technique.	VLSI	1999	DBLP BibTeX RDF
1	Edoardo Charbon, Joel R. Phillips	Substrate Noise: Analysis, Models, and Optimization.	VLSI	1999	DBLP BibTeX RDF

Publications at "VLSI"( http://dblp.L3S.de/Venues/VLSI )