Search results for "IEEE J. Solid State Circuits"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Chunxiao Hu, Diyang Zheng, Yun Yin, Jie Lin, Yicheng Li, Wei Li 0038, Hongtao Xu	A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Yoontae Jung, Sein Oh, Sohmyung Ha, Minkyu Je	A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Kristof Dens, Joren Vaes, Christian Blümm, Gabriel Guimaraes, Berke Gungor, Changsong Xie, Alexander Dyck, Patrick Reynaert	Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Liang Gao 0005, Chi Hou Chan	A 144-Element Beam-Steerable Source Array With 9.1-dBm Radiated Power and 30.8-dBm Lensless EIPR at 675 GHz.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Kyeongho Eom, Han-Sol Lee, Minju Park, Seung Min Yang, Jong Chan Choe, Suk-Won Hwang, Young-Woo Suh, Hyung-Min Lee	A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Yan Lu 0002, Shaolan Li	Guest Editorial 2023 Custom Integrated Circuits Conference.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang 0009, Weiwei Shan	A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim	A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He	A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Junyao Tang, Lei Zhao, Cheng Huang 0004	A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC-DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Tuur Van Daele, Filip Tavernier	Monolithic 230-VRMS-to-12-VDC AC-DC Converter at 9 mW/mm2 Enabled by a 31-325-VDC Input Range Capacitive Multi-Ratio DC-DC Converter.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Shuangxing Zhao, Chenchang Zhan, Yan Lu 0002	A Battery-Input Three-Mode Buck-Boost Hybrid DC-DC Converter With 97.6% Peak Efficiency.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Eunseok Lee 0002, Muhammad Ibrahim Wasiq Khan, Xibi Chen, Utsav Banerjee, Nathan M. Monroe, Rabia Tugce Yazicigil, Ruonan Han 0001, Anantha P. Chandrakasan	A 1.54-mm2, 264-GHz Wake-Up Receiver With Integrated Cryptographic Authentication for Ultra-Miniaturized Platforms.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Chuxiong Lin, Weifeng He, Yanan Sun 0003, Lin Shao, Bo Zhang, Jun Yang 0006, Mingoo Seok	A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Chia-Chi Kuo, Rihito Kuroda	A 134×132 4-Tap CMOS Indirect Time-of-Flight Range Imager Using In-Pixel Memory Array With 10 Kfps High-Speed Mode and High Precision Mode.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Junjie Wang 0008, Teng Zhang, Shuang Liu, Yihe Liu, Yuancong Wu, Shaogang Hu, Tupei Chen, Yang Liu 0062, Yuchao Yang, Ru Huang	Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Martijn Timmermans, Kyle van Oosterhout, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore	A 1.8-65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Milad Moosavifar, Jaeho Im, David D. Wentzloff	An Interference-Resilient Bit-Level Duty-Cycled ULP Receiver Leveraging a Dual-Chirp Modulation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Murali Krishna Rajendran, Priya Venugopal, Gajendranath Chowdary	An Incremental Step Sensing MPPT Based SI-SIDO Energy Harvester With >99% Peak MPPT Efficiency for an Input Power Range of 30 μW to 33 mW.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Fu-Bin Yang, Dao-Han Yao, Po-Hung Chen	A Quad-Mode Structure-Reconfigurable Regulating Rectifier With Shared-Inductor DC-DC Energy Recycling in a Wireless Power Receiver.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Mohammadreza Abbasi, Wooram Lee	A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jooyoung Bae, Wonsik Oh, Jahyun Koo 0003, Chengshuo Yu, Bongjin Kim	CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jungho Lee, Joseph G. Letner, Jongyup Lim, Gabriele Atzeni, Jiawei Liao, Abhilasha Kamboj, Bhavika Mani, Seokhyeon Jeong, Yejoong Kim, Yi Sun, Beomseo Koo, Julianna M. Richie, Elena Della Valle, Paras R. Patel, Dennis Sylvester, Hun-Seok Kim, Taekwang Jang, Jamie Phillips, Cynthia A. Chestek, James D. Weiland, David T. Blaauw	A Sub-mm3 Wireless Neural Stimulator IC for Visual Cortical Prosthesis With Optical Power Harvesting and 7.5-kb/s Data Telemetry.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo	C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Heejin Yang, Ji-Hwan Seol, Rohit Rothe, Zichen Fan, Qirui Zhang 0001, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Carl D'heer, Patrick Reynaert	A Fully Integrated 135-GHz Direct-Digital 16-QAM Wireless and Dielectric Waveguide Link in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Qiqiao Wu, Yue Cao, Qing Luo, Haijun Jiang, Zhongze Han, Yongkang Han, Chunmeng Dou, Hangbing Lv, Qi Liu 0010, Jianguo Yang, Ming Liu 0022	A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury	A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jiamin Li, Yilong Dong, Longyang Lin, Joanne Si Ying Tan, Fong Jia Yi, Jerald Yoo	Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jongho Kim, Gyuchan Cho, Jintae Kim	A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen	Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Hadi Lotfi, Michal Kern, Qing Yang 0034, Thomas Unden, Nico Striegler, Jochen Scharpf, Patrick Schalberger, Rainer Stöhr, Ilai Schwartz, Philipp Neumann, Jens Anders	A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xiaoyu Guo, Hongge Li, Yuhao Chen	A 3.58 nJ/Node Dual Cross Correlation Analog-Front-End Circuit With ADC for Mutual Capacitive Panel.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Guansheng Lv, Wenhua Chen, Long Chen, Fadhel M. Ghannouchi, Zhenghe Feng	A 4.9-7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jianqiang Jiang, Junyao Tang, Lei Zhao, Chenchang Zhan, Cheng Huang 0004	A 63% Efficiency 1.29-W Single-Link Multiple-Output (SLiMO) Isolated DC-DC Converter Using FPC Micro-Transformer With Local Voltage and Global Power Regulations.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang 0050	A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo	DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Wei Tang 0010, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang	Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Arindam Mishra, Wei Zhu, Bernhard Wicht, Valentijn De Smedt	A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xiongjie Zhang, Qiaobo Ma, Yang Jiang 0002, Anyang Zhao, Man-Kay Law, Rui Paulo Martins, Pui-In Mak	An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and COUT-Free Operations.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Edward Liu, Hua Wang	A Broadband Four-Way Parallel-Series Doherty Power Amplifier for 5G Communications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj	Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	James Lin, Long Pham, Ran Tao, A. Gutmann, Shanglin Guo, Adam Cywar, Adam Spirer, Johan Mansson, Khiem Nguyen	A Low-Power, Wide-Bandwidth, Three-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Kenichi Okada	Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Caiyu Tong, Zihao Fan, Yuan Gao 0002	A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color Mixing Capability.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Hyo-Jin Park 0002, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Young-Jun Jeon, Jeeyoung Shin, Woong Choi, Junwon Jeong, Sung-Wan Hong	A Simultaneous Energy Transferring SIBO Converter Achieving Low Ripple and High Efficiency for AMOLED Applications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Lili Chen, Morteza Tavakoli Taba, Zainulabideen J. Khalifa, Andreia Cathelin, Ehsan Afshari	A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Christian Elgaard, Mustafa Özen, Eric Westesson, Ahmed Mahmoud, Florent Torres, Shakila Bint Reyaz, Therese Forsberg, Rehman Akbar, Hans Hagberg, Henrik Sjöland	Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jonas Pelgrims, Kris Myny, Wim Dehaene	An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim	A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Daniel Widmann, Tobias Tannert, Xuan-Quang Du, Thomas Veigel, Markus Grözing, Manfred Berroth	A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Jin-O. Seo, Mingoo Seok, SeongHwan Cho	A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Wei Xu, Zhijuan Li, Zetao Fang, Bo Wang 0012, Linze Hong, Gai Yang, Su-Ting Han, Xiaojin Zhao, Xiaoyi Wang	A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Khoi T. Phan, Yang Gao, Howard C. Luong	A 10.8-14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee	A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Yuanqing Huang, Yogesh Ramadass, Dongsheng Ma 0001	Design of Direct 48-V/1-V Three-Path Four-State Switching Power Converter With Adaptive VCF Rebalancing and Dual-Edge tdead Modulation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Kyeongwon Jeong, Sohmyung Ha, Minkyu Je	A 15.4-ENOB, Fourth-Order Truncation-Error-Shaping NS-SAR-Nested ΔΣ Modulator With Boosted Input Impedance and Range for Biosignal Acquisition.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Sijun Du, Bo Zhao 0003	A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin	A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Tao Wang, Jieyang Li, Di Hua, Liangbo Lei, Peng Cao, Peng Xu, Jiawei Xu 0001, Zhiliang Hong	A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Bo Zhang 0029, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao 0001, Afshin Momtaz	A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Dennis Sylvester	New Associate Editor.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Mike Shuo-Wei Chen, Visvesh S. Sathe 0001, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga	Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Li Wang 0083, Zhao Zhang 0004, Can Wang 0009, Rehan Azmat, Weimin Shi, C. Patrick Yue	A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Minju Park, Kyeongho Eom, Han-Sol Lee, Seung-Beom Ku, Hyung-Min Lee	A 9-V-Tolerant Stacked-Switched-Capacitor Stimulation System With Level-Adaptive Switch Control and Rapid Stimulus-Synchronized Charge Balancing for Implantable Devices.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Gabriele Atzeni, Can Livanelioglu, Sina Arjmandpour, Taekwang Jang	An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Antonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni	An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xichen Li, Yi-Hsiang Huang, Fucheng Yin, Jacques Christophe Rudell	A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew	A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Piotr Zbigniew Wieczorek, Krzysztof Starecki, Krzysztof Golofit, Maciej Radtke, Marcin Pilarz	A Thin Elastic NFC Forum Type 1 Compatible RFID Tag.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Tianxiang Qu, Peizhuo Wang, Liangbo Lei, Zhiliang Hong, Jiawei Xu 0001	A 136-GΩ Input-Impedance Active Electrode for Non-Contact Biopotential Signals Monitoring.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Haihua Li, Ka-Meng Lei, Rui Paulo Martins, Pui-In Mak	A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sheng-Yu Peng, I-Chun Liu, Yi-Heng Wu, Ting-Ju Lin, Chun-Jui Chen, Xiu-Zhu Li, Yong-Qi Cheng, Pin-Han Lin, Kuo-Hsuan Hung, Yu Tsao 0001	An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Chi-Wa U, Man-Kay Law, Rui Paulo Martins, Chi-Seng Lam	Sub-μW Auto-Calibration Bandgap Voltage Reference With 1σ Inaccuracy of ± 0.12% Within - 40°C to 120°C.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Jill C. Mayeda, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang 0008, Jian Pang, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada	A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Wei Song, Xiliang Liu, Heng Huang, Yusong Wu, Zijian Tang, Jintao Wang, Fengjun Ma, Jingfeng Zhou, Milin Zhang 0001	A Frequency-Division Transceiver for Long-Range Neural Signal Recording From Multiple Subjects.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xin Ming, Jian-Jun Kuang, Xin-Ce Gong, Jie Zhang 0068, Zhuo Wang 0007, Bo Zhang 0027	An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Mototsugu Hamada, Ron Kapusta	Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Cooper S. Levy, Zhe Xuan, Jahnavi Sharma, Duanni Huang, Ranjeet Kumar, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Jinyong Kim, Xinru Wu, Tolga Acikalin, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi	8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	ZiXuan Xu, Kai Xing, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan	An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Lili Chen, Andreia Cathelin, Ehsan Afshari	A High-Efficiency High-Power 170-176-GHz Frequency Stabilized Quadrature Radiator.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Chuan-Tung Lin, Dewei Wang, Bo Zhang, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok	DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sundeep Javvaji, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems	A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen 0033, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson 0002, William J. Dally, C. Thomas Gray	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Fei Tan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak	A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Moon Hyung Jang, Maddy Hays, Wei-Han Yu, Changuk Lee, Pietro Caragiulo, Athanasios T. Ramkaj, Pingyu Wang, A. J. Phillips, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore	A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Mostafa Essawy, Kareem Rashed, Amin Aghighi, Arun Natarajan 0001	A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Joydeep Basu, Luigi Fassio, Karim Ali 0004, Massimo Alioto	Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Dennis Sylvester	New Associate Editor.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sidharth Thomas, Sam Razavian, Jaskirat Singh Virdi, Wei Sun, Benyamin Fallahi Motlagh, Aydin Babakhani	A 400-GHz Efficient Radiator and OOK Transceiver for Multi-Gb/s Wireless Communication in Silicon.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh	A 46.6 μg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted Chopper Amplifier.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Liqun Feng, Woogeun Rhee, Zhihua Wang 0001	A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Xinling Yue, Sijun Du	Corrections to "A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting".	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Sai-Wang Tam, Alireza Razzaghi, Alden Wong, Sridhar Narravula, Weiwei Xu, Timothy Loo, Akash Kambale, Asish Lowrance, Ovidiu Carnu, Yui Lin, Randy Tsang	A 28 nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter With On-Chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Junsoo Kim 0002, Seunghee Han, Geonwoo Ko, Ji-Hoon Kim, Changha Lee, Taewoo Kim 0003, Chan-Hyun Youn, Joo-Young Kim 0001	EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Francesco Conti 0001, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
1	Seyed Mojtaba Sadati Faramarzi, Bin Luo, Jef Poortmans, Jan Genoe, Kris Myny	Thin-Film Transistor-Based Sensor Interface Circuits Enabling Distributed Local In-Module Solar Cell Temperature Monitoring.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF

Publications at "IEEE J. Solid State Circuits"( http://dblp.L3S.de/Venues/IEEE_J._Solid_State_Circuits )