| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Alon Ascoli, Ahmet Samil Demirkol, Ronald Tetzlaff, Leon O. Chua |
Edge of Chaos Theory Sheds Light Into the All-to-None Phenomenon in Neurons - Part I: On the Fundamental Role of the Sodium Ion Channel.  |
IEEE Trans. Circuits Syst. I Regul. Pap.  |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Sastry Garimella, Sasank Garikapati, Aravind Nagulu, Harish Krishnaswamy |
Passive Frequency Shifting of N-Path Filters Through Rotary Clocking: Analysis and Design. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Zhongyu Dai, Wenxi Peng, Zhenfa Wang, Musong Li, Yitong Zhou, Ran Wang, Ting Chen, Xian Zhang, Junhua Wang |
Reconfigurable Receiver With Adaptive Output Voltage for Wireless Power Transfer. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yihan Fu, Daijing Shi, Anjunyi Fan, Wenshuo Yue, Yuchao Yang, Ru Huang, Bonan Yan |
Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Shakti Singh, Rahul Shrestha |
A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Zhihong Liang, Sanbo Ding, Yan-Hui Jing 0001, Xiangpeng Xie |
Dual-Event-Driven Synchronization Control for Discrete-Time Complex Dynamical Networks. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Rongjiang Li, Guanpu Chen, Die Gan, Haibo Gu, Jinhu Lü |
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Pengcheng Chen, Shichao Liu 0001, Xiaozhe Wang, Innocent Kamwa |
Physics-Guided Multi-Agent Deep Reinforcement Learning for Robust Active Voltage Control in Electrical Distribution Systems. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Siyue Li, Shize Zhou, Yongqi Xue, Wenjie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li 0003, Yuxiang Fu |
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Dongmin Kim, Dongmyeong Kim, Ignacio Llamas-Garro, Donggu Im |
A Sub-GHz/2.4 GHz Highly Selective Reconfigurable RF Front-End Employing an N-Path Complementary Balun-LNA and Linearized RF-to-BB Current-Reuse Mixer. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Li Li 0043, Xudong Chen, Jing Liang, Hongguang Pan |
Stabilization and Synchronization Control of Multi Coupled Hyperbolic-Parabolic Partial Differential Systems Based on Backstepping Method. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yangyang Chen, Huiyu Feng, Suwen Song, Zhongfeng Wang 0001 |
Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO Systems. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse |
Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Liangyu Chen, Xiaoping Wang 0001, Chao Yang, Zhanfei Chen, Junming Zhang, Zhigang Zeng |
Full-Analog Reservoir Computing Circuit Based on Memristor With a Hybrid Wide-Deep Architecture. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandra L. Zimpeck, Alexander Fish |
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023). |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Baoting Li, Danqing Zhang, Pengfei Zhao, Hang Wang, Xuchong Zhang, Hongbin Sun 0001, Nanning Zheng 0001 |
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jialong Liu, Wenjun Tang, Hongtian Li, Deyun Chen, Weihang Long, Yongpan Liu, Chen Jiang, Huazhong Yang, Xueqing Li |
TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai |
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman |
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujuan Liu, Jiajun Ma, Chengkai Cui |
FPGA Implementation of Threshold Projection Orthogonal Matching Pursuit Algorithm for Compressed Sensing Reconstruction. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Alaa AbdAlRahman, Lobna A. Said, Ahmed Soltan, Ahmed G. Radwan |
Hardware Accelerator of Fractional-Order Operator Based on Phase Optimized Filters With Applications. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Morgana Macedo Azevedo da Rosa, Patrícia Ücker Leleu da Costa, Eduardo Antonio Cesar da Costa, Rafael Iankowski Soares, Sergio Bampi |
VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamza Errahmouni Barkam, Sanggeon Yun, Paul R. Genssler, Che-Kai Liu, Zhuowen Zou, Hussam Amrouch, Mohsen Imani |
In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu |
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Erica Raviola, Franco Fiori |
On the Damping of Ringing Affecting Power Transistors by Means of Active Gate Drivers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinming Lu, Hui Wang, Jun Lin 0001, Zhongfeng Wang 0001 |
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Saijin Huang, Tian Liang Guo, Xiangyu Wang 0003, Shihua Li 0001, Qi Li 0017 |
An Output Voltage Tracking Control Method With Overcurrent Protection Property for Disturbed DC-DC Boost Converters. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Wang 0094, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang |
Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Sergio Ruben Geninatti, Manuel Agustín Ortiz-López, Francisco Javier Quiles-Latorre, Tomás Morales-Leal, Andrés Gersnoviez, Antonio Moreno-Muñoz |
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Chia Hsu, Tian-Sheuan Chang |
ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingya Feng, Yongzhuang Wei, Fengrong Zhang, Enes Pasalic, Yu Zhou 0012 |
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Dinh Cong Huong, Van Thanh Huynh, Nguyen Gia Minh Thao, Tien Phuc Dang, Hieu Trinh |
State Estimation for a New Battery and Motor Circuit Model of an Electric Vehicle Using Event-Triggered Functional Interval Observers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianchi Ye, Kaixuan Ye, Ziying Xie, Min Tan 0004 |
A Four-Channel TDM Clocked-Analog LDO Using a Shared Compensation Block for Thermo-Optic Tuning. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li 0004, Runsheng Wang, Yuan Wang 0001 |
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Kim Allinger, Andreas Bahr, Matthias Kuhl |
Modeling of CMOS Integrated Strain Sensors and Sensitivity Enhanced Readout Architecture. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Maite Martincorena-Arraiza, Carlos Aristoteles De la Cruz-Blas, Alfonso Carlosena |
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Kai Hsu, Vaidehi Garg, Anni Lu, Shimeng Yu |
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen 0007, Jianyu Guo, Ruili Ren, Zhangming Zhu |
A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuel Escudero, Sabina Spiga, Mauro Di Marco, Mauro Forti, Giacomo Innocenti, Alberto Tesi, Fernando Corinto, Stefano Brivio |
Chua's Circuit With Tunable Nonlinearity Based on a Nonvolatile Memristor: Design and Realization. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr Walid, Dadian Zhou, Jose Silva-Martinez |
Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu |
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Damiano Rotondo, Didier Theilliol, Jean-Christophe Ponsart |
Virtual Actuator and Sensor Fault Tolerant Consensus for Homogeneous Linear Multi-Agent Systems. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Meixuan Jade Li, Chi K. Tse |
Where Should Inverter-Based Resources Be Located in Power Networks? |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Guansheng Lv, Wenhua Chen, Xiaofan Chen, Fadhel M. Ghannouchi, Zhenghe Feng |
A 1.8-5.4-GHz GaN MMIC Distributed Efficient Power Amplifier With Reactance Compensation and Adaptive Biasing. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Wu, Yong Chen 0005, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang 0014 |
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Huihong Shi, Yang Xu, Yuefei Wang, Wendong Mao, Zhongfeng Wang 0001 |
NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Yushen Hu, Tin Shing Peter Ho, Tengteng Lei, Zhihe Xia, Man Wong |
Construction and Application of a Neuromorphic Circuit With Excitatory and Inhibitory Post-Synaptic Conduction Channels Implemented Using Dual-Gate Thin-Film Transistors. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Bi Wu, Tianyang Yu, Ke Chen 0018, Weiqiang Liu 0001 |
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Keun Ahn, Sumin Lee, Seong-Ook Jung |
A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Pandaram, Paul R. Genssler, Hussam Amrouch |
WaSSaBi: Wafer Selection With Self-Supervised Representations and Brain-Inspired Active Learning. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenhai Qi, Ning Zhang, Guangdeng Zong, Choon Ki Ahn |
SMC for Discrete Semi-Markov Switching Slow Sampling Singularly Perturbed Models With Applications. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolai Fiege, Martin Kumm, Peter Zipf |
Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Zhiwen Gu, Yuhang Zhang, Yang Zhao, Jinghua Zhang, Yanhan Zeng, Zhihong Luo, Yongfu Li 0002 |
Synthesizing Step-Down Switched Capacitor Power Converter Topologies. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Inbal Stanger, Noam Roknian, Netanel Shavit, Yonatan Shoshan, Yoav Weizman, Adam Teman, Edoardo Charbon, Alexander Fish |
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Bowen Wang, Cong Ding 0004, Yunzhao Nie, Woogeun Rhee, Zhihua Wang 0001 |
A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiyu Qian, Yongrong Shi, Juan Han, Shijie Liu, Yifan Guo, Longbao Cheng, Yongjiu Zhao, Tangsheng Chen |
X-Band Power Divider Design and Its Network for Active Electronically Scanned Array Vertical Integration. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Nivedita Rai, Sandeep Semwal, Rohit Kumar Nirala, Abhinav Kranti |
Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Xiaofei Wang, Jing Jin 0005, Xiaoming Liu 0008, Hui Wang 0023, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou |
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Sekeon Kim, Sehee Lim, Dong Han Ko, Tae Woo Oh, Seong-Ook Jung |
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakesh Sinha |
Correction to "Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks". |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Amin Faraji, Sayed Alireza Sadrossadat, Jing Jin, Weicong Na, Feng Feng, Qi-Jun Zhang |
Hybrid Batch-Normalized Deep Feedforward Neural Network Incorporating Polynomial Regression for High-Dimensional Microwave Modeling. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerd Kiene, Ramon W. J. Overwater, Masoud Babaie, Fabio Sebastiano |
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Bhogi Satya Swaroop, Ayush Saxena, Shubham Sahay |
Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng 0002, Xiaoyang Zeng, Jun Han 0003 |
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jia Yao, Xiaofeng Zheng, Zihao Luo, Zeyv Zhang, Adrian Ioinovici |
A Switched Capacitor Modified Fibonacci Cell Used for a DC-AC Circuit Supplied by Solar Energy. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Fabiha Nowshin, Yi Huang 0008, Md. Rubel Sarkar, Qiangfei Xia, Yang Yi 0002 |
MERRC: A Memristor-Enabled Reconfigurable Low-Power Reservoir Computing Architecture at the Edge. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Zijing Niu, Tingting Zhang, Honglan Jiang, Bruce F. Cockburn, Leibo Liu, Jie Han 0001 |
Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jun Mou, Tao Ma, Santo Banerjee, Yushu Zhang |
A Novel Memcapacitive-Synapse Neuron: Bionic Modeling, Complex Dynamics Analysis and Circuit Implementation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Da Ming, Yuhang Wang, Zhicheng Wang, Ken Xingze Wang, Ciyuan Qiu, Min Tan 0004 |
EPHIC Models: General SPICE Photonic Models for Closed-Loop Electronic-Photonic Co-Simulation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Tianqi Kong, Shuguo Li |
Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Sung Hyun You, Sang Su Lee, Sun Lim, Seok-Kyoon Kim, Choon Ki Ahn |
Model-Free Filter for Servo Drive Applications via Error Dynamics Diagonalization Technique. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Lei Shi 0012, Zhuangzhuang Ma, Shuaiming Yan, Tianyong Ao |
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Shivam Prakash Gautam, Manish Kumar Barwar, Lalit Kumar Sahu, Satyajit Mohanty, Santanu Kumar Dash 0002, Kashem M. Muttaqi |
A Bidirectional Single Capacitor Unit Based Hybrid T-Type Converter Topology With Sensor-Less Voltage Balancing Capabilities. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Sayed Alireza Sajjadi, Sayed Alireza Sadrossadat, Ali Moftakharzadeh, Morteza Nabavi, Mohamad Sawan |
DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Baoping Ren, Xinlei Liu, Xuehui Guan, Haiwen Liu |
High-Order HTS Dual-Band Differential Bandpass Filter Using Stub-Loaded Twin-Ring Resonator With Fully Controllable Passbands. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Shikai Chen, Yanfeng Chen, Bo Zhang 0011, Dongyuan Qiu |
Stability Analysis for On-Off Voltage-Mode Controlled VHF Converter Combining Short-Period and Long-Period Discrete Map Models. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Christopher Grimm, Jinseok Lee, Naveen Verma |
Training Neural Networks With In-Memory-Computing Hardware and Multi-Level Radix-4 Inputs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Sidou Zheng, Xiaoyue Xia, Rong Lu, Si-Yuan Tang, Zekun Li 0005, Rui Zhou, Peigen Zhou, Debin Hou, Jixin Chen, Wei Hong 0002 |
A 94-GHz 16T1R Hybrid Integrated Phased Array With ±50° Scanning Range for High-Date-Rate Communication. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Xin Zhao, Liang Chang 0002, Dongqi Fan, Zhicheng Hu, Ting Yue, Fengbin Tu, Jun Zhou 0017 |
HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jie Lou, Florian Freye, Christian Lanius, Tobias Gemmeke |
An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Minsik Kim, Kyoungseok Oh, Youngmock Cho, Hojin Seo, Xuan Truong Nguyen, Hyuk-Jae Lee |
A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Bao Zhao, Jiacong Qiu, Junrui Liang |
Circuit Solutions Toward Broadband Piezoelectric Energy Harvesting: An Impedance Analysis. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Siyuan Wei, Ke Ning, Lei Kang, Xuemin Zheng, Mingxin Zhao, Mengmeng Xu, Shuyu Wang, Xuanzhe Xu, Runjiang Dou, Shuangming Yu, Xu Yang 0017, Jian Liu 0021, Cong Shi 0003, Nanjian Wu, Liyuan Liu |
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | José M. de la Rosa 0001 |
Incoming Editorial. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jie Zhou 0026, Bingzheng Yang, Yiyang Shu, Xun Luo |
A W-Band 2 × 2 Phased-Array Transmitter With Digital Gain-Compensation Technique. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Adriaan Peetermans, Ingrid Verbauwhede |
Characterization of Oscillator Phase Noise Arising From Multiple Sources for ASIC True Random Number Generation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Chensheng Liu, Yuanqi Li, Hongcheng Zhu, Yang Tang, Wenli Du |
Parameter-Estimate-First False Data Injection Attacks in AC State Estimation Deployed With Moving Target Defense. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Yonghua Wang 0001, Zheliang Zhang, Yongwei Zhang 0002, Mingming Liang, Derong Liu 0001 |
A Novel Online Adaptive Dynamic Programming Algorithm With Adjustable Convergence Rate. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Heng You, Weijun Li, Delong Shang, Yumei Zhou, Shushan Qiao |
A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Meixuan Jade Li, Chi K. Tse, Ming Yi |
Steady-State Cascading Failure Model With Voltage Instability Event Detection. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Wente Yi, Kefan Mo, Wenjia Wang, Yitong Zhou, Yejun Zeng, Zihan Yuan, Bojun Cheng, Biao Pan |
RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Tun-Hao Yang, Tian-Sheuan Chang |
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator With Decoupled Asymmetric Convolution. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Jie Deng, Pascal Burasa, Ke Wu |
Self-Contained Dual-Input Interferometric Receiver for Paralleled-Multichannel Wireless Systems. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Javad Gorji, Shanthi Pavan, José M. de la Rosa 0001 |
On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Bo Xu, Hang Geng, Leping Jiang, Songting Zou, Kai Chen 0018, Zhen Liu 0003 |
FPGA Implementation of Memristor Emulators Using Fractional Order Calculus: A High-Precision Reconfigurable Approach. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Li Dang, Shubin Liu, Ruixue Ding, Yi Shen 0007, Zhangming Zhu |
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang 0011, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang 0001 |
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Ying Zhao 0010, Donghui Wu, Changyi Xu, Shuanghe Yu, Tianhe Liu, Dong Yang 0007 |
Adaptive Anti-Disturbance Bumpless Transfer Control for Switched Neural Network Systems With Its Application to Switched Circuit Model. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Nitish Jolly, Ayan Mallik |
Parasitic Mismatch Mitigation for Fast Switching Modular Power Semiconductor Devices. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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| 1 | Hongling Qiu, Jun Shen 0002, Jinde Cao, Heng Liu 0003 |
L∞-Gain of Fractional-Order Positive Systems With Mixed Time-Varying Delays. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
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