Search results for "IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."

Hits ?▲	Authors	Title	Venue	Year	Link
1	Xing Huang, Huayang Cai, Wenzhong Guo, Genggeng Liu, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann	Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yixuan Wang 0001, Weichao Zhou, Jiameng Fan, Zhilu Wang, Jiajun Li, Xin Chen 0002, Chao Huang 0015, Wenchao Li 0001, Qi Zhu 0002	POLAR-Express: Efficient and Precise Formal Reachability Analysis of Neural-Network Controlled Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yiwen Zhang 0002, Jin-Peng Ma, Hui Zheng, Zonghua Gu 0001	Criticality-Aware EDF Scheduling for Constrained-Deadline Imprecise Mixed-Criticality Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Zeming Cheng, Bo Zhang 0098, Massoud Pedram	A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Israel F. Araujo, Carsten Blank, Ismael C. S. Araujo, Adenilton J. da Silva	Low-Rank Quantum State Preparation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Cong Wang, Dongen Yang, Jinming Lyu, Yong Dai, Cheng Zhuo, Quan Chen	On Model Order Reduction and Exponential Integrator for Transient Circuit Simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hayoung Lee, Sooryeong Lee, Sungho Kang 0001	A New Fail Address Memory Architecture for Cost-Effective ATE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jiandong Mu, Mengdi Wang, Feiwen Zhu, Jun Yang, Wei Lin 0016, Wei Zhang 0012	Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen 0001, Yi Kang	NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xiaoqiang Tang, Antonio Raffo, Nicola Donato, Giovanni Crupi, Jialin Cai	Theoretical and Experimental Analysis of a CSWPL Behavioral Model for Microwave GaN Transistors Including DC Bias Voltages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Liqiang Lu, Zizhang Luo, Size Zheng 0001, Jieming Yin, Jason Cong, Yun Liang 0001, Jianwei Yin	Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chen Yang 0005, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng	Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hyunsu Chae, Keren Zhu 0001, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan	ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Laleh Behjat, José Luís Güntzel	ILPGRC: ILP-Based Global Routing Optimization With Cell Movements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xiaoxiao Liang, Yikang Ouyang, Haoyu Yang, Bei Yu 0001, Yuzhe Ma	RL-OPC: Mask Optimization With Deep Reinforcement Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jie Zhang 0081, Hongjing Huang, Jie Sun 0017, Juan Gómez-Luna, Onur Mutlu, Zeke Wang	SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jinyu Bai, Sifan Sun, Weisheng Zhao, Wang Kang 0001	CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Lu Li, Guofeng Qin, Yang Yu 0008, Weijia Wang 0003	Compact Instruction Set Extensions for Kyber.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yufei Chen, Zizheng Guo, Runsheng Wang, Ru Huang, Yibo Lin, Cheng Zhuo	Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang 0001, Bei Yu 0001, Martin D. F. Wong	L2O-ILT: Learning to Optimize Inverse Lithography Techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Wonyoung Lee 0001, Mincheol Kang, Soontae Kim	Highly VM-Scalable SSD in Cloud Storage Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Burin Amornpaisannon, Andreas Diavastos, Li-Shiuan Peh, Trevor E. Carlson	Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	João Batista Pereira Matos Jr., Eddie B. de Lima Filho, Iury Bessa, Edoardo Manino, Xidan Song, Lucas C. Cordeiro	Counterexample Guided Neural Network Quantization Refinement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hao Ding 0007, Yanlong He, Zhongyi Zhai, Zhi Li 0017, Junyan Qian, Lingzhong Zhao	Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Zhenge Jia, Dawei Li, Cong Liu, Liqi Liao, Xiaowei Xu 0004, Lichuan Ping, Yiyu Shi 0001	TinyML Design Contest for Life-Threatening Ventricular Arrhythmia Detection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Tuo Dai, Bizhao Shi, Guojie Luo	Weave: Abstraction and Integration Flow for Accelerators of Generated Modules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Runze Wang, Ao Hu, Long Zheng 0003, Qinggang Wang, Jingrui Yuan, Haifeng Liu 0003, Linchen Yu, Xiaofei Liao, Hai Jin 0001	An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Zheng Xiao, Weijie Chen, Yunchuan Qin, Fan Wu, Anthony Theodore Chronopoulos, Alex Nicolau, Kenli Li 0001	NGLIC: A Nonaligned-Row Legalization Approach for 3-D Interdie Connection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chao Xiao, Xu He, Zhijie Yang, Xun Xiao, Yao Wang 0002, Rui Gong, Junbo Tie, Lei Wang 0011, Weixia Xu	Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Sven Thijssen, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz	PATH: Evaluation of Boolean Logic Using Path-Based In-Memory Computing Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Arman Roohi, Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi	PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Sen Yin, Ruitao Wang, Jian Zhang, Xiaosen Liu, Yan Wang 0023	Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Test Insertion for Dynamic Test Compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo 0004, Qianming Yang, Li Shen 0007, Gang Chen 0023, Liquan Xiao, Nong Xiao	A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Cheng-Yun Hsieh, Hsin-Ying Tsai, Yuan-Hsiang Lu, James Chien-Mo Li	Small Sampling Overhead Error Mitigation for Quantum Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Quan Nguyen-Gia, Hyungcheol Shin	Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Fangzhou Wang, Jinwei Liu, Wing Ho Lau, Haocheng Li, Evangeline F. Y. Young	FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks 0001, Gu-Yeon Wei, Vijay Janapa Reddi	Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Haihua Hu, Guojun Han, Wenhua Wu 0002, Chang Liu 0008	Channel Parameter and Read Reference Voltages Estimation in 3-D NAND Flash Memory Using Unsupervised Learning Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon	PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Longfei Luo, Dingcui Yu, Hang Li, Yunpeng Song, Yina Lv, Edwin H.-M. Sha, Liang Shi	Revisiting TRIM on High-Density Flash-Based Hybrid Storage Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Liang Chang 0002, Hang Lu, Chenglong Li, Xin Zhao, Zhicheng Hu, Jun Zhou 0017, Xiaowei Li 0001	General Purpose Deep Learning Accelerator Based on Bit Interleaving.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Weihong Liu, Jiawei Geng, Zongwei Zhu, Yang Zhao, Cheng Ji, Changlong Li, Zirui Lian, Xuehai Zhou	Ace-Sniper: Cloud-Edge Collaborative Scheduling Framework With DNN Inference Latency Modeling on Heterogeneous Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Ran Wei, Zhe Jiang 0004, Xiaoran Guo, Ruizhe Yang, Haitao Mei, Athanasios Zolotas, Tim Kelly	DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Guanglong Li, Yaoyao Ye	HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jie Zou, Xiaotian Dai 0001, John A. McDermid	Context-Aware Graceful Degradation for Mixed-Criticality Scheduling in Autonomous Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Daijoon Hyun, Younggwang Jung, Youngsoo Shin	Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jinming Zhang, Xi Fan, Yaoyao Ye, Xuyan Wang, Guojie Xiong, Xianglun Leng, Ningyi Xu, Yong Lian 0001, Guanghui He	INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xiaoyu Sun 0001, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang	Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yao Tong, Quan Chen	Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Mengquan Li, Kenli Li 0001, Chao Wu 0006, Gang Liu, Mingfeng Lan, Yunchuan Qin, Zhuo Tang, Weichen Liu	Automated Optical Accelerator Search Toward Superior Acceleration Efficiency, Inference Robustness, and Development Speed.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jie Yang, Kai Qiao, Shuhao Shi, Baojie Song, Jian Chen 0025, Bin Yan 0002	AEM-PCB Reverser: Circuit Schematic Generation in PCB Reverse Engineering Using Reinforcement Learning Based on Aesthetic Evaluation Metric.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Pruthvy Yellu, Nishanth Goud Chennagouni, Qiaoyan Yu	INEAD: Intermediate Node Evaluation-Based Attack Detection for Secure Approximate Computing Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Tunhou Zhang, Jiang Hu, Yiran Chen 0001	Toward Fully Automated Machine Learning for Routability Estimator Development.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Shamiul Alam, William Mitchell Hunter, Nazmul Amin, Md. Mazharul Islam 0006, Sumeet Kumar Gupta, Ahmedullah Aziz	Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Duo Wang, Mingyu Yan, Yihan Teng, Dengke Han, Xin Liu 0073, Wenming Li, Xiaochun Ye, Dongrui Fan	MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yiwen Zhang 0002, Hui Zheng, Zonghua Gu 0001	EDF-Based Energy-Efficient Semi-Clairvoyant Scheduling With Graceful Degradation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Tianyu Wang, Zizhan Chen, Wenbin Zhu, Qian Wei, Zhaoyan Shen, Zili Shao	A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Luca Sterpone, Sarah Azimi, Corrado De Sio	CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Long Zheng 0003, Ao Hu, Qinggang Wang, Yu Huang 0013, Haoqin Huang, Pengcheng Yao, Shuyi Xiong, Xiaofei Liao, Hai Jin 0001	PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Wenjie Li 0003, Aokun Hu, Ningyi Xu, Guanghui He	A Precision-Scalable Deep Neural Network Accelerator With Activation Sparsity Exploitation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Shuai Yang, Wei Zi, Bujiao Wu, Cheng Guo, Jialin Zhang 0001, Xiaoming Sun 0001	Efficient Quantum Circuit Synthesis for SAT-Oracle With Limited Ancillary Qubit.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hongyang Pan, Yinshui Xia, Lunyao Wang, Zhufei Chu	Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Kyeonghyeon Baek, Taewhan Kim	CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Renaud Gillon, Franco Fummi	Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Michael Vera-Panez, Kewin Cuadros-Claro, Manuel Castillo-Cara, Luis Orozco-Barbosa	BeeGOns!: A Wireless Sensor Node for Fog Computing in Smart City Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Keyu Peng, Wenxing Zhu	Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Minhui Zou, Zhenhua Zhu, Tzofnat Greenberg-Toledo, Orian Leitersdorf, Jiang Li, Junlong Zhou, Yu Wang 0002, Nan Du, Shahar Kvatinsky	TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Kaniz Mishty, Mehdi Sadi	System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Donglei Wu, Weihao Yang, Haoyu Jin, Xiangyu Zou, Wen Xia, Binxing Fang	FedComp: A Federated Learning Compression Framework for Resource-Constrained Edge Computing Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Dongdong Zhao, Weibo Mao, Peng Chen 0008, Yingtian Hu, Haoran Liang, Yuanjie Dang, Ronghua Liang, Xinxin Guo	A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Li Lu, Junchao Chen 0001, Markus Ulbricht 0002, Milos Krstic	Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Wei Chen 0100, Dake Liu	Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang 0001, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu 0001, Zaikun Zhang, Xuan Zeng 0001	BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski	Generation of Two-Cycle Tests for Structurally Similar Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu	DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xinmiao Zhang, Cheng Liu 0008, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li 0001, Xiaowei Li 0001	PDG: A Prefetcher for Dynamic Graph Updating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Pei Yuan, Jonathan Allcock, Shengyu Zhang	Does Qubit Connectivity Impact Quantum Circuit Complexity?	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Binhao Bao, Qianhui Li, Wu Guan, Qi Wang, Liping Liang, Xin Qiu	Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jiajun Zhou, Jiajun Wu 0006, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong	DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chandramouli N. Amarnath, Mohamed Mejri, Kwondo Ma, Abhijit Chatterjee	Error Resilience in Deep Neural Networks Using Neuron Gradient Statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Vedika Saravanan, Samah Mohamed Saeed	Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jingyu Pan, Xuezhong Lin, Jinming Xu 0002, Yiran Chen 0001, Cheng Zhuo	Lithography Hotspot Detection Based on Heterogeneous Federated Learning With Local Adaptation and Feature Selection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang 0006, Yao-Wen Chang	High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang	Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Sai Pentapati, Kyungwook Chang, Sung Kyu Lim	Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Soomin Kim, Taewhan Kim	Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Ayesha Siddique, Khaza Anuarul Hoque	Moving Target Defense Through Approximation for Low-Power Neuromorphic Edge Intelligence.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Yu-Guang Chen, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann	Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Rassul Bairamkulov, Eby G. Friedman	Power Aware Placement of On-Chip Voltage Regulators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu	Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chen Yin, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing	DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Dmitrii Kirov, Pierluigi Nuzzo 0002, Alberto L. Sangiovanni-Vincentelli, Roberto Passerone	Efficient Encodings for Scalable Exploration of Cyber-Physical System Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xiaoze Lin, Liyang Lai, Huawei Li 0001	Parallel Static Learning Toward Heterogeneous Computing Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Lihao Liu, Fan Yang 0001, Li Shang, Xuan Zeng 0001	GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang 0001	Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Jasmin Kaur, Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh	Hardware Constructions for Error Detection in WG-29 Stream Cipher Benchmarked on FPGA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Hongyan Li, Hang Lu, Xiaowei Li 0001	Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
1	Xiaohui Wei, Nan Jiang, Hengshan Yue, Xiaonan Wang, Jianpeng Zhao, Guangli Li, Meikang Qiu	ApproxDup: Developing an Approximate Instruction Duplication Mechanism for Efficient SDC Detection in GPGPUs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF

Publications at "IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."( http://dblp.L3S.de/Venues/IEEE_Trans._Comput._Aided_Des._Integr._Circuits_Syst. )